Merge branch 'for-next/zynq'

20 files changed, 147 insertions, 600 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 372257413d..dfb18777b2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -253,6 +253,7 @@ config ARCH_UEMD
 config ARCH_ZYNQ
 	bool "Xilinx Zynq-based boards"
 	select HAS_DEBUG_LL
+	select PBL_IMAGE
 
 config ARCH_ZYNQMP
 	bool "Xilinx ZynqMP-based boards"
diff --git a/arch/arm/boards/avnet-zedboard/Makefile b/arch/arm/boards/avnet-zedboard/Makefile
index a2c3104e6c..01c7a259e9 100644
--- a/arch/arm/boards/avnet-zedboard/Makefile
+++ b/arch/arm/boards/avnet-zedboard/Makefile
@@ -1,3 +1,2 @@
 obj-y += board.o
 lwl-y += lowlevel.o
-lwl-y += flash_header.o
diff --git a/arch/arm/boards/avnet-zedboard/board.c b/arch/arm/boards/avnet-zedboard/board.c
index 722bda302e..f53dde47c2 100644
--- a/arch/arm/boards/avnet-zedboard/board.c
+++ b/arch/arm/boards/avnet-zedboard/board.c
@@ -17,38 +17,14 @@
 #include <environment.h>
 #include <generated/mach-types.h>
 #include <init.h>
-#include <mach/devices.h>
 #include <mach/zynq7000-regs.h>
 #include <linux/sizes.h>
 
-static int zedboard_mem_init(void)
-{
-	arm_add_mem_device("ram0", 0, SZ_512M);
-
-	return 0;
-}
-mem_initcall(zedboard_mem_init);
-
-static struct macb_platform_data macb_pdata = {
-	.phy_interface = PHY_INTERFACE_MODE_RGMII,
-	.phy_addr = 0x0,
-};
-
-static int zedboard_device_init(void)
-{
-	zynq_add_eth0(&macb_pdata);
-
-	return 0;
-}
-device_initcall(zedboard_device_init);
 
 static int zedboard_console_init(void)
 {
-	barebox_set_model("Avnet ZedBoard");
 	barebox_set_hostname("zedboard");
 
-	zynq_add_uart1();
-
 	return 0;
 }
 console_initcall(zedboard_console_init);
diff --git a/arch/arm/boards/avnet-zedboard/flash_header.c b/arch/arm/boards/avnet-zedboard/flash_header.c
deleted file mode 100644
index d9eb35b0d5..0000000000
--- a/arch/arm/boards/avnet-zedboard/flash_header.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (C) 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <common.h>
-#include <asm/byteorder.h>
-#include <mach/zynq-flash-header.h>
-#include <mach/zynq7000-regs.h>
-#include <asm/barebox-arm-head.h>
-
-#define REG(a, v) { .addr = cpu_to_le32(a), .val = cpu_to_le32(v), }
-
-struct zynq_reg_entry __ps7reg_entry_section reg_entry[] = {
-	REG(ZYNQ_SLCR_UNLOCK, 0x0000DF0D),
-	REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_CLK_621_TRUE, 0x00000001),
-	REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_APER_CLK_CTRL, 0x01FC044D),
-
-	REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028008),
-	REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CFG, 0x000FA220),
-	REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028010),
-	REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028011),
-	REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028010),
-	REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028000),
-
-	REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CTRL, 0x0001E008),
-	REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CFG, 0x001452C0),
-	REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CTRL, 0x0001E010),
-	REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CTRL, 0x0001E011),
-	REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CTRL, 0x0001E010),
-	REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CTRL, 0x0001E000),
-
-	REG(0xf8000150, 0x00000a03),
-
-	/* stop */
-	REG(0xFFFFFFFF, 0x00000000),
-};
-
-struct zynq_flash_header __flash_header_section flash_header = {
-	.width_det		= WIDTH_DETECTION_MAGIC,
-	.image_id		= IMAGE_IDENTIFICATION,
-	.enc_stat		= 0x0,
-	.user			= 0x0,
-	.flash_offset		= 0x8c0,
-	.length			= (unsigned int)&_barebox_image_size,
-	.res0			= 0x0,
-	.start_of_exec		= 0x0,
-	.total_len		= (unsigned int)&_barebox_image_size,
-	.res1			= 0x1,
-	.checksum		= 0x0,
-	.res2			= 0x0,
-};
diff --git a/arch/arm/boards/avnet-zedboard/lowlevel.c b/arch/arm/boards/avnet-zedboard/lowlevel.c
index cf3c4ebd0c..93e4da96ec 100644
--- a/arch/arm/boards/avnet-zedboard/lowlevel.c
+++ b/arch/arm/boards/avnet-zedboard/lowlevel.c
@@ -27,8 +27,13 @@
 #define PLL_DDR_LOCK	(1 << 1)
 #define PLL_IO_LOCK	(1 << 2)
 
-void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
+extern char __dtb_zynq_zed_start[];
+
+ENTRY_FUNCTION(start_avnet_zedboard, r0, r1, r2)
 {
+
+	void *fdt = __dtb_zynq_zed_start + get_runtime_offset();
+
 	/* open sesame */
 	writel(0x0000DF0D, ZYNQ_SLCR_UNLOCK);
 
@@ -257,5 +262,6 @@ void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
 	writel(0x0000767B, ZYNQ_SLCR_LOCK);
 
 	arm_cpu_lowlevel_init();
-	barebox_arm_entry(0, SZ_512M, NULL);
+
+	barebox_arm_entry(0, SZ_512M, fdt);
 }
diff --git a/arch/arm/boards/avnet-zedboard/zedboard.zynqcfg b/arch/arm/boards/avnet-zedboard/zedboard.zynqcfg
new file mode 100644
index 0000000000..3f8808d3d7
--- /dev/null
+++ b/arch/arm/boards/avnet-zedboard/zedboard.zynqcfg
@@ -0,0 +1,24 @@
+#include <mach/zynq7000-header-regs.h>
+
+wm 32 ZYNQ_SLCR_UNLOCK		0x0000DF0D
+wm 32 ZYNQ_CLK_621_TRUE		0x00000001
+wm 32 ZYNQ_APER_CLK_CTRL	0x01FC044D
+
+wm 32 ZYNQ_ARM_PLL_CTRL		0x00028008
+wm 32 ZYNQ_ARM_PLL_CFG		0x000FA220
+wm 32 ZYNQ_ARM_PLL_CTRL		0x00028010
+wm 32 ZYNQ_ARM_PLL_CTRL		0x00028011
+wm 32 ZYNQ_ARM_PLL_CTRL		0x00028010
+wm 32 ZYNQ_ARM_PLL_CTRL		0x00028000
+
+wm 32 ZYNQ_IO_PLL_CTRL		0x0001E008
+wm 32 ZYNQ_IO_PLL_CFG		0x001452C0
+wm 32 ZYNQ_IO_PLL_CTRL		0x0001E010
+wm 32 ZYNQ_IO_PLL_CTRL		0x0001E011
+wm 32 ZYNQ_IO_PLL_CTRL		0x0001E010
+wm 32 ZYNQ_IO_PLL_CTRL		0x0001E000
+
+wm 32 ZYNQ_SDIO_CLK_CTRL	0x00000a03
+
+/* stop */
+wm 32 0xFFFFFFFF			0x00000000
\ No newline at end of file
diff --git a/arch/arm/configs/zedboard_defconfig b/arch/arm/configs/zynq_defconfig
index cc03368751..a16c57d5ce 100644
--- a/arch/arm/configs/zedboard_defconfig
+++ b/arch/arm/configs/zynq_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARCH_ZYNQ=y
+CONFIG_MACH_ZEDBOARD=y
 CONFIG_AEABI=y
 CONFIG_ARM_UNWIND=y
-CONFIG_PBL_IMAGE=y
 CONFIG_MMU=y
 CONFIG_STACK_SIZE=0xf000
 CONFIG_MALLOC_SIZE=0x8000000
@@ -40,6 +40,8 @@ CONFIG_CMD_OFTREE=y
 CONFIG_CMD_TIME=y
 CONFIG_NET=y
 CONFIG_DRIVER_SERIAL_CADENCE=y
+CONFIG_DRIVER_NET_MACB=y
 # CONFIG_SPI is not set
+# CONFIG_PINCTRL is not set
 CONFIG_FS_TFTP=y
 CONFIG_DIGEST=y
diff --git a/arch/arm/configs/zynqmp_defconfig b/arch/arm/configs/zynqmp_defconfig
index 834212e30f..762103c541 100644
--- a/arch/arm/configs/zynqmp_defconfig
+++ b/arch/arm/configs/zynqmp_defconfig
@@ -33,7 +33,9 @@ CONFIG_CMD_TIMEOUT=y
 CONFIG_CMD_CLK=y
 CONFIG_CMD_OFTREE=y
 CONFIG_CMD_TIME=y
+CONFIG_NET=y
 CONFIG_DRIVER_SERIAL_CADENCE=y
+CONFIG_DRIVER_NET_MACB=y
 # CONFIG_SPI is not set
-CONFIG_FIRMWARE_ZYNQMP_PL=y
+CONFIG_FIRMWARE_ZYNQMP_FPGA=y
 CONFIG_DIGEST=y
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9566e97555..5c9a311c5f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -144,5 +144,6 @@ lwl-dtb-$(CONFIG_MACH_ZII_IMX7D_DEV) += imx7d-zii-rpu2.dtb.o imx7d-zii-rmu2.dtb.
 lwl-dtb-$(CONFIG_MACH_WAGO_PFC_AM35XX) += am35xx-pfc-750_820x.dtb.o
 lwl-dtb-$(CONFIG_MACH_LS1046ARDB) += fsl-ls1046a-rdb.dtb.o
 lwl-dtb-$(CONFIG_MACH_TQMLS1046A) += fsl-tqmls1046a-mbls10xxa.dtb.o
+lwl-dtb-$(CONFIG_MACH_ZEDBOARD) += zynq-zed.dtb.o
 
 clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts *.dtb.lzo
diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts
new file mode 100644
index 0000000000..52d6833249
--- /dev/null
+++ b/arch/arm/dts/zynq-zed.dts
@@ -0,0 +1,7 @@
+#include <arm/zynq-zed.dts>
+
+/ {
+	chosen {
+		stdout-path = &uart1;
+	};
+};
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index d35bd41232..3e07633e5f 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -2,34 +2,33 @@ if ARCH_ZYNQ
 
 config ARCH_TEXT_BASE
 	hex
-	default 0x1ff00000 if MACH_ZEDBOARD
+	default 0x0
 
 config ZYNQ_DEBUG_LL_UART_BASE
 	hex
 	default 0xe0001000 if MACH_ZEDBOARD
 
-choice
-	prompt "Xilinx Zynq type board"
-
 config ARCH_ZYNQ7000
-	bool "Zynq-7000"
+	bool
 	select CPU_V7
 	select CLKDEV_LOOKUP
 	select COMMON_CLK
+	select COMMON_CLK_OF_PROVIDER
 	select ARM_SMP_TWD
 	select HAS_MACB
+	select HAVE_PBL_MULTI_IMAGES
+	select OFTREE
+	select OFDEVICE
+	select RELOCATABLE
 
-endchoice
 
-if ARCH_ZYNQ7000
 
-choice
-	prompt "Zynq-7000 Board Type"
+menu "select Zynq boards to be built"
 
 config MACH_ZEDBOARD
 	bool "Avnet Zynq-7000 ZedBoard"
+	select ARCH_ZYNQ7000
 
-endchoice
-endif
+endmenu
 
 endif
diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile
index 459c957622..3252247d17 100644
--- a/arch/arm/mach-zynq/Makefile
+++ b/arch/arm/mach-zynq/Makefile
@@ -1 +1 @@
-obj-y += zynq.o devices.o clk-zynq7000.o
+obj-y += zynq.o
diff --git a/arch/arm/mach-zynq/clk-zynq7000.c b/arch/arm/mach-zynq/clk-zynq7000.c
deleted file mode 100644
index cd49d8478f..0000000000
--- a/arch/arm/mach-zynq/clk-zynq7000.c
+++ /dev/null
@@ -1,426 +0,0 @@
-/*
- * Copyright (c) 2013 Josh Cartwright <joshc@eso.teric.us>
- * Copyright (c) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de>
- *
- * Based on drivers/clk-zynq.c from Linux.
- *
- * Copyright (c) 2012 National Instruments
- *
- * Josh Cartwright <josh.cartwright@ni.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-#include <common.h>
-#include <init.h>
-#include <io.h>
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/err.h>
-#include <mach/zynq7000-regs.h>
-#include <malloc.h>
-
-enum zynq_clks {
-	dummy, ps_clk, arm_pll, ddr_pll, io_pll, uart_clk, uart0, uart1,
-	cpu_clk, cpu_6x4x, cpu_3x2x, cpu_2x, cpu_1x,
-	gem_clk, gem0, gem1, clks_max
-};
-
-enum zynq_pll_type {
-	ZYNQ_PLL_ARM,
-	ZYNQ_PLL_DDR,
-	ZYNQ_PLL_IO,
-};
-
-#define PLL_STATUS_ARM_PLL_LOCK		(1 << 0)
-#define PLL_STATUS_DDR_PLL_LOCK		(1 << 1)
-#define PLL_STATUS_IO_PLL_LOCK		(1 << 2)
-#define PLL_STATUS_ARM_PLL_STABLE	(1 << 0)
-#define PLL_STATUS_DDR_PLL_STABLE	(1 << 1)
-#define PLL_STATUS_IO_PLL_STABLE	(1 << 2)
-#define PLL_CTRL_BYPASS_FORCE		(1 << 4)
-
-static struct clk *clks[clks_max];
-
-struct zynq_pll_clk {
-	struct clk	clk;
-	u32		pll_lock;
-	void __iomem	*pll_ctrl;
-};
-
-#define to_zynq_pll_clk(c)	container_of(c, struct zynq_pll_clk, clk)
-
-#define PLL_CTRL_FDIV(x)	(((x) >> 12) & 0x7F)
-
-static unsigned long zynq_pll_recalc_rate(struct clk *clk,
-					  unsigned long parent_rate)
-{
-	struct zynq_pll_clk *pll = to_zynq_pll_clk(clk);
-	return parent_rate * PLL_CTRL_FDIV(readl(pll->pll_ctrl));
-}
-
-static int zynq_pll_enable(struct clk *clk)
-{
-	struct zynq_pll_clk *pll = to_zynq_pll_clk(clk);
-	u32 val;
-	int timeout = 10000;
-
-	val = readl(pll->pll_ctrl);
-	val &= ~PLL_CTRL_BYPASS_FORCE;
-	writel(val, pll->pll_ctrl);
-
-	while (timeout--) {
-		if (readl(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_PLL_STATUS) & pll->pll_lock)
-			break;
-	}
-
-	if (!timeout)
-		return -ETIMEDOUT;
-
-	return 0;
-}
-
-static struct clk_ops zynq_pll_clk_ops = {
-	.recalc_rate = zynq_pll_recalc_rate,
-	.enable = zynq_pll_enable,
-};
-
-static inline struct clk *zynq_pll_clk(enum zynq_pll_type type,
-				       const char *name,
-				       void __iomem *pll_ctrl)
-{
-	static const char *pll_parent = "ps_clk";
-	struct zynq_pll_clk *pll;
-	int ret;
-
-	pll = xzalloc(sizeof(*pll));
-	pll->pll_ctrl		= pll_ctrl;
-	pll->clk.ops		= &zynq_pll_clk_ops;
-	pll->clk.name		= name;
-	pll->clk.parent_names	= &pll_parent;
-	pll->clk.num_parents	= 1;
-
-	switch(type) {
-	case ZYNQ_PLL_ARM:
-		pll->pll_lock = PLL_STATUS_ARM_PLL_LOCK;
-		break;
-	case ZYNQ_PLL_DDR:
-		pll->pll_lock = PLL_STATUS_DDR_PLL_LOCK;
-		break;
-	case ZYNQ_PLL_IO:
-		pll->pll_lock = PLL_STATUS_IO_PLL_LOCK;
-		break;
-	}
-
-	ret = clk_register(&pll->clk);
-	if (ret) {
-		free(pll);
-		return ERR_PTR(ret);
-	}
-
-	return &pll->clk;
-}
-
-struct zynq_periph_clk {
-	struct clk	clk;
-	void __iomem	*clk_ctrl;
-};
-
-#define to_zynq_periph_clk(c)  container_of(c, struct zynq_periph_clk, c)
-
-static const u8 periph_clk_parent_map[] = {
-	0, 0, 1, 2
-};
-#define PERIPH_CLK_CTRL_SRC(x) (periph_clk_parent_map[((x) & 0x30) >> 4])
-#define PERIPH_CLK_CTRL_DIV(x) (((x) & 0x3F00) >> 8)
-
-static unsigned long zynq_periph_recalc_rate(struct clk *clk,
-					     unsigned long parent_rate)
-{
-	struct zynq_periph_clk *periph = to_zynq_periph_clk(clk);
-	return parent_rate / PERIPH_CLK_CTRL_DIV(readl(periph->clk_ctrl));
-}
-
-static int zynq_periph_get_parent(struct clk *clk)
-{
-	struct zynq_periph_clk *periph = to_zynq_periph_clk(clk);
-	return PERIPH_CLK_CTRL_SRC(readl(periph->clk_ctrl));
-}
-
-static const struct clk_ops zynq_periph_clk_ops = {
-	.recalc_rate	= zynq_periph_recalc_rate,
-	.get_parent	= zynq_periph_get_parent,
-};
-
-static struct clk *zynq_periph_clk(const char *name, void __iomem *clk_ctrl)
-{
-	static const char *peripheral_parents[] = {
-		"io_pll",
-		"arm_pll",
-		"ddr_pll",
-	};
-	struct zynq_periph_clk *periph;
-	int ret;
-
-	periph = xzalloc(sizeof(*periph));
-
-	periph->clk_ctrl	= clk_ctrl;
-	periph->clk.name	= name;
-	periph->clk.ops		= &zynq_periph_clk_ops;
-	periph->clk.parent_names = peripheral_parents;
-	periph->clk.num_parents	= ARRAY_SIZE(peripheral_parents);
-
-	ret = clk_register(&periph->clk);
-	if (ret) {
-		free(periph);
-		return ERR_PTR(ret);
-	}
-
-	return &periph->clk;
-}
-
-/* CPU Clock domain is modelled as a mux with 4 children subclks, whose
- * derivative rates depend on CLK_621_TRUE
- */
-
-struct zynq_cpu_clk {
-	struct clk	clk;
-	void __iomem	*clk_ctrl;
-};
-
-#define to_zynq_cpu_clk(c)	container_of(c, struct zynq_cpu_clk, c)
-
-static const u8 zynq_cpu_clk_parent_map[] = {
-	1, 1, 2, 0
-};
-#define CPU_CLK_SRCSEL(x)	(zynq_cpu_clk_parent_map[(((x) & 0x30) >> 4)])
-#define CPU_CLK_CTRL_DIV(x)	(((x) & 0x3F00) >> 8)
-
-static unsigned long zynq_cpu_clk_recalc_rate(struct clk *clk,
-					      unsigned long parent_rate)
-{
-	struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(clk);
-	return parent_rate / CPU_CLK_CTRL_DIV(readl(cpuclk->clk_ctrl));
-}
-
-static int zynq_cpu_clk_get_parent(struct clk *clk)
-{
-	struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(clk);
-	return CPU_CLK_SRCSEL(readl(cpuclk->clk_ctrl));
-}
-
-static const struct clk_ops zynq_cpu_clk_ops = {
-	.get_parent	= zynq_cpu_clk_get_parent,
-	.recalc_rate	= zynq_cpu_clk_recalc_rate,
-};
-
-static struct clk *zynq_cpu_clk(const char *name, void __iomem *clk_ctrl)
-{
-	static const char *cpu_parents[] = {
-		"io_pll",
-		"arm_pll",
-		"ddr_pll",
-	};
-	struct zynq_cpu_clk *cpu;
-	int ret;
-
-	cpu = xzalloc(sizeof(*cpu));
-
-	cpu->clk_ctrl		= clk_ctrl;
-	cpu->clk.ops		= &zynq_cpu_clk_ops;
-	cpu->clk.name		= name;
-	cpu->clk.parent_names	= cpu_parents;
-	cpu->clk.num_parents	= ARRAY_SIZE(cpu_parents);
-
-	ret = clk_register(&cpu->clk);
-	if (ret) {
-		free(cpu);
-		return ERR_PTR(ret);
-	}
-
-	return &cpu->clk;
-}
-
-enum zynq_cpu_subclk_which {
-	CPU_SUBCLK_6X4X,
-	CPU_SUBCLK_3X2X,
-	CPU_SUBCLK_2X,
-	CPU_SUBCLK_1X,
-};
-
-struct zynq_cpu_subclk {
-	struct clk	clk;
-	void __iomem	*clk_ctrl;
-	void __iomem	*clk_621;
-	enum zynq_cpu_subclk_which which;
-};
-
-#define CLK_621_TRUE(x)		((x) & 1)
-
-#define to_zynq_cpu_subclk(c)	container_of(c, struct zynq_cpu_subclk, c);
-
-static unsigned long zynq_cpu_subclk_recalc_rate(struct clk *clk,
-						 unsigned long parent_rate)
-{
-	unsigned long uninitialized_var(rate);
-	struct zynq_cpu_subclk *subclk;
-	bool is_621;
-
-	subclk = to_zynq_cpu_subclk(clk);
-	is_621 = CLK_621_TRUE(readl(subclk->clk_621));
-
-	switch (subclk->which) {
-	case CPU_SUBCLK_6X4X:
-		rate = parent_rate;
-		break;
-	case CPU_SUBCLK_3X2X:
-		rate = parent_rate / 2;
-		break;
-	case CPU_SUBCLK_2X:
-		rate = parent_rate / (is_621 ? 3 : 2);
-		break;
-	case CPU_SUBCLK_1X:
-		rate = parent_rate / (is_621 ? 6 : 4);
-		break;
-	};
-
-	return rate;
-}
-
-static int zynq_cpu_subclk_enable(struct clk *clk)
-{
-	struct zynq_cpu_subclk *subclk;
-	u32 tmp;
-
-	subclk = to_zynq_cpu_subclk(clk);
-
-	tmp = readl(subclk->clk_ctrl);
-	tmp |= 1 << (24 + subclk->which);
-	writel(tmp, subclk->clk_ctrl);
-
-	return 0;
-}
-
-static void zynq_cpu_subclk_disable(struct clk *clk)
-{
-	struct zynq_cpu_subclk *subclk;
-	u32 tmp;
-
-	subclk = to_zynq_cpu_subclk(clk);
-
-	tmp = readl(subclk->clk_ctrl);
-	tmp &= ~(1 << (24 + subclk->which));
-	writel(tmp, subclk->clk_ctrl);
-}
-
-static const struct clk_ops zynq_cpu_subclk_ops = {
-	.enable		= zynq_cpu_subclk_enable,
-	.disable	= zynq_cpu_subclk_disable,
-	.recalc_rate	= zynq_cpu_subclk_recalc_rate,
-};
-
-static struct clk *zynq_cpu_subclk(const char *name,
-				   enum zynq_cpu_subclk_which which,
-				   void __iomem *clk_ctrl,
-				   void __iomem *clk_621)
-{
-	static const char *subclk_parent = "cpu_clk";
-	struct zynq_cpu_subclk *subclk;
-	int ret;
-
-	subclk = xzalloc(sizeof(*subclk));
-
-	subclk->clk_ctrl	= clk_ctrl;
-	subclk->clk_621		= clk_621;
-	subclk->which		= which;
-	subclk->clk.name	= name;
-	subclk->clk.ops		= &zynq_cpu_subclk_ops;
-
-	subclk->clk.parent_names = &subclk_parent;
-	subclk->clk.num_parents	= 1;
-
-	ret = clk_register(&subclk->clk);
-	if (ret) {
-		free(subclk);
-		return ERR_PTR(ret);
-	}
-
-	return &subclk->clk;
-}
-
-static int zynq_clock_probe(struct device_d *dev)
-{
-	struct resource *iores;
-	void __iomem *slcr_base;
-	unsigned long ps_clk_rate = 33333330;
-
-	iores = dev_request_mem_resource(dev, 0);
-	if (IS_ERR(iores))
-		return PTR_ERR(iores);
-	slcr_base = IOMEM(iores->start);
-
-	clks[ps_clk]  = clk_fixed("ps_clk", ps_clk_rate);
-
-	clks[arm_pll] = zynq_pll_clk(ZYNQ_PLL_ARM, "arm_pll", slcr_base + 0x100);
-	clks[ddr_pll] = zynq_pll_clk(ZYNQ_PLL_DDR, "ddr_pll", slcr_base + 0x104);
-	clks[io_pll]  = zynq_pll_clk(ZYNQ_PLL_IO,  "io_pll", slcr_base + 0x108);
-
-	clks[uart_clk] = zynq_periph_clk("uart_clk", slcr_base + 0x154);
-
-	clks[uart0] = clk_gate("uart0", "uart_clk", slcr_base + 0x154, 0, 0, 0);
-	clks[uart1] = clk_gate("uart1", "uart_clk", slcr_base + 0x154, 1, 0, 0);
-
-	clks[gem0] = clk_gate("gem0", "io_pll", slcr_base + 0x140, 0, 0, 0);
-	clks[gem1] = clk_gate("gem1", "io_pll", slcr_base + 0x144, 1, 0, 0);
-
-	clks[cpu_clk] = zynq_cpu_clk("cpu_clk", slcr_base + 0x120);
-
-	clks[cpu_6x4x] = zynq_cpu_subclk("cpu_6x4x", CPU_SUBCLK_6X4X,
-					slcr_base + 0x120, slcr_base + 0x1C4);
-	clks[cpu_3x2x] = zynq_cpu_subclk("cpu_3x2x", CPU_SUBCLK_3X2X,
-					slcr_base + 0x120, slcr_base + 0x1C4);
-	clks[cpu_2x] = zynq_cpu_subclk("cpu_2x", CPU_SUBCLK_2X,
-					slcr_base + 0x120, slcr_base + 0x1C4);
-	clks[cpu_1x] = zynq_cpu_subclk("cpu_1x", CPU_SUBCLK_1X,
-					slcr_base + 0x120, slcr_base + 0x1C4);
-
-	clk_register_clkdev(clks[cpu_3x2x], NULL, "arm_smp_twd");
-	clk_register_clkdev(clks[uart0], NULL, "zynq_serial0");
-	clk_register_clkdev(clks[uart1], NULL, "zynq_serial1");
-	clk_register_clkdev(clks[gem0], NULL, "macb0");
-	clk_register_clkdev(clks[gem1], NULL, "macb1");
-
-	clkdev_add_physbase(clks[cpu_3x2x], CORTEXA9_SCU_TIMER_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[uart1], ZYNQ_UART1_BASE_ADDR, NULL);
-
-	return 0;
-}
-
-static __maybe_unused struct of_device_id zynq_clock_dt_ids[] = {
-	{
-		.compatible = "xlnx,zynq-clock",
-	}, {
-		/* sentinel */
-	}
-};
-
-static struct driver_d zynq_clock_driver = {
-	.probe  = zynq_clock_probe,
-	.name   = "zynq-clock",
-	.of_compatible = DRV_OF_COMPAT(zynq_clock_dt_ids),
-};
-
-static int zynq_clock_init(void)
-{
-	return platform_driver_register(&zynq_clock_driver);
-}
-postcore_initcall(zynq_clock_init);
diff --git a/arch/arm/mach-zynq/devices.c b/arch/arm/mach-zynq/devices.c
deleted file mode 100644
index 55e9433c51..0000000000
--- a/arch/arm/mach-zynq/devices.c
+++ /dev/null
@@ -1,13 +0,0 @@
-#include <common.h>
-#include <driver.h>
-#include <mach/devices.h>
-
-struct device_d *zynq_add_uart(resource_size_t base, int id)
-{
-	return add_generic_device("cadence-uart", id, NULL, base, 0x1000, IORESOURCE_MEM, NULL);
-}
-
-struct device_d *zynq_add_eth(resource_size_t base, int id, struct macb_platform_data *pdata)
-{
-	return add_generic_device("macb", id, NULL, base, 0x1000, IORESOURCE_MEM, pdata);
-}
diff --git a/arch/arm/mach-zynq/include/mach/barebox.lds.h b/arch/arm/mach-zynq/include/mach/barebox.lds.h
deleted file mode 100644
index 3d35fe9880..0000000000
--- a/arch/arm/mach-zynq/include/mach/barebox.lds.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#define PRE_IMAGE \
-	.pre_image : {					\
-		. = 0x20;				\
-		KEEP(*(.flash_header_0x0*))		\
-		. = 0xa0;				\
-		KEEP(*(.ps7reg_entry_0x0A0))		\
-		. = 0x8c0;				\
-	}
diff --git a/arch/arm/mach-zynq/include/mach/devices.h b/arch/arm/mach-zynq/include/mach/devices.h
deleted file mode 100644
index c9670b02f3..0000000000
--- a/arch/arm/mach-zynq/include/mach/devices.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#include <mach/zynq7000-regs.h>
-#include <platform_data/macb.h>
-
-struct device_d *zynq_add_uart(resource_size_t base, int id);
-struct device_d *zynq_add_eth(resource_size_t base, int id, struct macb_platform_data *pdata);
-
-static inline struct device_d *zynq_add_uart0(void)
-{
-	return zynq_add_uart((resource_size_t)ZYNQ_UART0_BASE_ADDR, 0);
-}
-
-static inline struct device_d *zynq_add_uart1(void)
-{
-	return zynq_add_uart((resource_size_t)ZYNQ_UART1_BASE_ADDR, 1);
-}
-
-static inline struct device_d *zynq_add_eth0(struct macb_platform_data *pdata)
-{
-	return zynq_add_eth((resource_size_t)ZYNQ_GEM0_BASE_ADDR, 0, pdata);
-}
diff --git a/arch/arm/mach-zynq/include/mach/zynq-flash-header.h b/arch/arm/mach-zynq/include/mach/zynq-flash-header.h
index 3b67e55a71..ba4b67f479 100644
--- a/arch/arm/mach-zynq/include/mach/zynq-flash-header.h
+++ b/arch/arm/mach-zynq/include/mach/zynq-flash-header.h
@@ -1,38 +1,27 @@
 #ifndef __MACH_FLASH_HEADER_H
 #define __MACH_FLASH_HEADER_H
 
-#include <asm-generic/sections.h>
+#include <stdint.h>
 
-#define __flash_header_section		__section(.flash_header_0x0)
-#define __ps7reg_entry_section		__section(.ps7reg_entry_0x0A0)
-#define __image_len_section		__section(.image_len_0x08c0)
-#define FLASH_HEADER_OFFSET		0x0
+#define REGINIT_OFFSET			0x0a0
 #define IMAGE_OFFSET			0x8c0
 
-#define DEST_BASE			0x8c0
-#define FLASH_HEADER_BASE	(DEST_BASE + FLASH_HEADER_OFFSET)
-
-struct zynq_reg_entry {
-	__le32 addr;
-	__le32 val;
-};
-
 #define WIDTH_DETECTION_MAGIC	0xAA995566
 #define IMAGE_IDENTIFICATION	0x584C4E58	/* "XLNX" */
 
 struct zynq_flash_header {
-	__le32 width_det;
-	__le32 image_id;
-	__le32 enc_stat;
-	__le32 user;
-	__le32 flash_offset;
-	__le32 length;
-	__le32 res0;
-	__le32 start_of_exec;
-	__le32 total_len;
-	__le32 res1;
-	__le32 checksum;
-	__le32 res2;
+	uint32_t width_det;
+	uint32_t image_id;
+	uint32_t enc_stat;
+	uint32_t user;
+	uint32_t flash_offset;
+	uint32_t length;
+	uint32_t res0;
+	uint32_t start_of_exec;
+	uint32_t total_len;
+	uint32_t res1;
+	uint32_t checksum;
+	uint32_t res2;
 };
 
 #endif /* __MACH_FLASH_HEADER_H */
diff --git a/arch/arm/mach-zynq/include/mach/zynq7000-header-regs.h b/arch/arm/mach-zynq/include/mach/zynq7000-header-regs.h
new file mode 100644
index 0000000000..4e24064746
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/zynq7000-header-regs.h
@@ -0,0 +1,49 @@
+/*
+ * (c) 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define ZYNQ_SLCR_LOCK			0xF8000004
+#define ZYNQ_SLCR_UNLOCK		0xF8000008
+#define ZYNQ_ARM_PLL_CTRL		0xF8000100
+#define ZYNQ_DDR_PLL_CTRL		0xF8000104
+#define ZYNQ_IO_PLL_CTRL		0xF8000108
+#define ZYNQ_PLL_STATUS			0xF800010C
+#define ZYNQ_ARM_PLL_CFG		0xF8000110
+#define ZYNQ_DDR_PLL_CFG		0xF8000114
+#define ZYNQ_IO_PLL_CFG			0xF8000118
+#define ZYNQ_ARM_CLK_CTRL		0xF8000120
+#define ZYNQ_DDR_CLK_CTRL		0xF8000124
+#define ZYNQ_DCI_CLK_CTRL		0xF8000128
+#define ZYNQ_APER_CLK_CTRL		0xF800012C
+#define ZYNQ_USB0_CLK_CTRL		0xF8000130
+#define ZYNQ_USB1_CLK_CTRL		0xF8000134
+#define ZYNQ_GEM0_RCLK_CTRL		0xF8000138
+#define ZYNQ_GEM1_RCLK_CTRL		0xF800013C
+#define ZYNQ_GEM0_CLK_CTRL		0xF8000140
+#define ZYNQ_GEM1_CLK_CTRL		0xF8000144
+#define ZYNQ_SMC_CLK_CTRL		0xF8000148
+#define ZYNQ_LQSPI_CLK_CTRL		0xF800014C
+#define ZYNQ_SDIO_CLK_CTRL		0xF8000150
+#define ZYNQ_UART_CLK_CTRL		0xF8000154
+#define ZYNQ_SPI_CLK_CTRL		0xF8000158
+#define ZYNQ_CAN_CLK_CTRL		0xF800015C
+#define ZYNQ_CAN_MIOCLK_CTRL	0xF8000160
+#define ZYNQ_DBG_CLK_CTRL		0xF8000164
+#define ZYNQ_PCAP_CLK_CTRL		0xF8000168
+#define ZYNQ_TOPSW_CLK_CTRL		0xF800016C
+#define ZYNQ_FPGA0_CLK_CTRL		0xF8000170
+#define ZYNQ_FPGA1_CLK_CTRL		0xF8000180
+#define ZYNQ_FPGA2_CLK_CTRL		0xF8000190
+#define ZYNQ_FPGA3_CLK_CTRL		0xF80001A0
+#define ZYNQ_CLK_621_TRUE		0xF80001C4
diff --git a/arch/arm/mach-zynq/include/mach/zynq7000-regs.h b/arch/arm/mach-zynq/include/mach/zynq7000-regs.h
index dd02f5b407..eeecfe1ded 100644
--- a/arch/arm/mach-zynq/include/mach/zynq7000-regs.h
+++ b/arch/arm/mach-zynq/include/mach/zynq7000-regs.h
@@ -63,6 +63,7 @@
 #define ZYNQ_FPGA3_CLK_CTRL		0x0A0
 #define ZYNQ_CLK_621_TRUE		0x0C4
 #define ZYNQ_RST_CTRL_BASE		(ZYNQ_SLCR_BASE + 0x200)
+#define ZYNQ_SLCR_BOOT_MODE		(ZYNQ_SLCR_BASE + 0x25C)
 #define ZYNQ_PSS_RST_CTRL		(ZYNQ_RST_CTRL_BASE + 0x000)
 #define ZYNQ_DDR_RST_CTRL		(ZYNQ_RST_CTRL_BASE + 0x004)
 #define ZYNQ_TOPSW_RST_CTRL		(ZYNQ_RST_CTRL_BASE + 0x008)
diff --git a/arch/arm/mach-zynq/zynq.c b/arch/arm/mach-zynq/zynq.c
index f6112fd249..79a6b908e0 100644
--- a/arch/arm/mach-zynq/zynq.c
+++ b/arch/arm/mach-zynq/zynq.c
@@ -14,11 +14,12 @@
  */
 
 #include <asm/system.h>
-#include <io.h>
+#include <bootsource.h>
 #include <common.h>
 #include <init.h>
-#include <restart.h>
+#include <io.h>
 #include <mach/zynq7000-regs.h>
+#include <restart.h>
 
 static void __noreturn zynq_restart_soc(struct restart_handler *rst)
 {
@@ -30,6 +31,26 @@ static void __noreturn zynq_restart_soc(struct restart_handler *rst)
 	hang();
 }
 
+static enum bootsource zynq_bootsource_get(void)
+{
+	u32 boot_mode = readl(ZYNQ_SLCR_BOOT_MODE);
+
+	switch (boot_mode & 0x7) {
+	case 0x0:
+		return BOOTSOURCE_JTAG;
+	case 0x1:
+		return BOOTSOURCE_SPI;
+	case 0x2:
+		return BOOTSOURCE_NOR;
+	case 0x4:
+		return BOOTSOURCE_NAND;
+	case 0x5:
+		return BOOTSOURCE_MMC;
+	default:
+		return BOOTSOURCE_UNKNOWN;
+	}
+}
+
 static int zynq_init(void)
 {
 	u32 val;
@@ -48,11 +69,10 @@ static int zynq_init(void)
 	writel(val, 0xf8f00000);
 	dmb();
 
-	add_generic_device("zynq-clock", 0, NULL, ZYNQ_SLCR_BASE, 0x4000, IORESOURCE_MEM, NULL);
-	add_generic_device("smp_twd", 0, NULL, CORTEXA9_SCU_TIMER_BASE_ADDR,
-				0x4000, IORESOURCE_MEM, NULL);
 	restart_handler_register_fn(zynq_restart_soc);
 
+	bootsource_set(zynq_bootsource_get());
+
 	return 0;
 }
 postcore_initcall(zynq_init);