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authorSascha Hauer <s.hauer@pengutronix.de>2020-02-11 09:36:54 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2020-02-19 08:30:31 +0100
commit8764645099f700b38198294c5f68ecb2f380944e (patch)
tree6e80857b54ac92555dddf320d0418052dfbc437e /arch
parent40f6bd8cdd1914fd77de3b35933a2195b92c8d7f (diff)
downloadbarebox-8764645099f700b38198294c5f68ecb2f380944e.tar.gz
ARM: i.MX8M: Add imx8mm-regs.h
Add various base addresses for the i.MX8MM. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-imx/include/mach/imx8mm-regs.h46
1 files changed, 46 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/include/mach/imx8mm-regs.h b/arch/arm/mach-imx/include/mach/imx8mm-regs.h
new file mode 100644
index 0000000..1325c78
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/imx8mm-regs.h
@@ -0,0 +1,46 @@
+#ifndef __MACH_IMX8MM_REGS_H
+#define __MACH_IMX8MM_REGS_H
+
+#include <mach/imx8m-regs.h>
+
+#define MX8MM_M4_BOOTROM_BASE_ADDR 0x007e0000
+
+#define MX8MM_GPIO1_BASE_ADDR 0x30200000
+#define MX8MM_GPIO2_BASE_ADDR 0x30210000
+#define MX8MM_GPIO3_BASE_ADDR 0x30220000
+#define MX8MM_GPIO4_BASE_ADDR 0x30230000
+#define MX8MM_GPIO5_BASE_ADDR 0x30240000
+#define MX8MM_WDOG1_BASE_ADDR 0x30280000
+#define MX8MM_WDOG2_BASE_ADDR 0x30290000
+#define MX8MM_WDOG3_BASE_ADDR 0x302a0000
+#define MX8MM_IOMUXC_BASE_ADDR 0x30330000
+#define MX8MM_IOMUXC_GPR_BASE_ADDR 0x30340000
+#define MX8MM_OCOTP_BASE_ADDR 0x30350000
+#define MX8MM_ANATOP_BASE_ADDR 0x30360000
+#define MX8MM_CCM_BASE_ADDR 0x30380000
+#define MX8MM_SRC_BASE_ADDR 0x30390000
+#define MX8MM_GPC_BASE_ADDR 0x303a0000
+#define MX8MM_SYSCNT_RD_BASE_ADDR 0x306a0000
+#define MX8MM_SYSCNT_CMP_BASE_ADDR 0x306b0000
+#define MX8MM_SYSCNT_CTRL_BASE_ADDR 0x306c0000
+#define MX8MM_UART1_BASE_ADDR 0x30860000
+#define MX8MM_UART3_BASE_ADDR 0x30880000
+#define MX8MM_UART2_BASE_ADDR 0x30890000
+#define MX8MM_I2C1_BASE_ADDR 0x30a20000
+#define MX8MM_I2C2_BASE_ADDR 0x30a30000
+#define MX8MM_I2C3_BASE_ADDR 0x30a40000
+#define MX8MM_I2C4_BASE_ADDR 0x30a50000
+#define MX8MM_UART4_BASE_ADDR 0x30a60000
+#define MX8MM_USDHC1_BASE_ADDR 0x30b40000
+#define MX8MM_USDHC2_BASE_ADDR 0x30b50000
+#define MX8MM_USDHC3_BASE_ADDR 0x30b60000
+#define MX8MM_USB1_BASE_ADDR 0x32e40000
+#define MX8MM_USB2_BASE_ADDR 0x32e50000
+#define MX8MM_TZASC_BASE_ADDR 0x32f80000
+#define MX8MM_SRC_IPS_BASE_ADDR 0x30390000
+#define MX8MM_SRC_DDRC_RCR_ADDR 0x30391000
+#define MX8MM_SRC_DDRC2_RCR_ADDR 0x30391004
+#define MX8MM_DDRC_DDR_SS_GPR0 0x3d000000
+#define MX8MM_DDR_CSD1_BASE_ADDR 0x40000000
+
+#endif /* __MACH_IMX8MM_REGS_H */