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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2020-06-17 18:05:03 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2020-06-18 14:12:01 +0200 |
| commit | 93651898a5d6a2ab5c0e947f759ea55e82564b54 (patch) | |
| tree | 82e259ac050bff0a7e1968c47871dad8d9b42c7e /arch | |
| parent | 6c1e7688df94a9d4dfebeb62266f7fc91c209d8a (diff) | |
| download | barebox-93651898a5d6a2ab5c0e947f759ea55e82564b54.tar.gz barebox-93651898a5d6a2ab5c0e947f759ea55e82564b54.tar.xz | |
Arm: i.MX5: Do not disable L2 cache
Disabling the L2 cache is not working in imx5_init_lowlevel() because
the necessary cache maintenance operations are missing. This often
results in cache corruption in a chainloaded barebox.
Disabling the cache is unnecessary: when we come from the ROM the L2
cache is disabled anyway, so disabling it is a no-op. When we get here
in a chainloaded barebox the L2 cache is already enabled and correctly
configured. So instead of initializing it again we can take an enabled
L2 cache as a sign to skip initialization and just return from the
function.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/imx5.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm/mach-imx/imx5.c b/arch/arm/mach-imx/imx5.c index 96288f99e0..dd6c079fe3 100644 --- a/arch/arm/mach-imx/imx5.c +++ b/arch/arm/mach-imx/imx5.c @@ -37,10 +37,13 @@ void imx5_init_lowlevel(void) { u32 r; - /* ARM errata ID #468414 */ __asm__ __volatile__("mrc 15, 0, %0, c1, c0, 1":"=r"(r)); + + if (r & (1 << 1)) + return; + + /* ARM errata ID #468414 */ r |= (1 << 5); /* enable L1NEON bit */ - r &= ~(1 << 1); /* explicitly disable L2 cache */ __asm__ __volatile__("mcr 15, 0, %0, c1, c0, 1" : : "r"(r)); /* reconfigure L2 cache aux control reg */ |