diff options
| author | Andrey Smirnov <andrew.smirnov@gmail.com> | 2018-06-12 11:47:52 -0700 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-06-13 09:56:21 +0200 |
| commit | a9fe1f9be67408f21800a99cbd8c5399ee3297f0 (patch) | |
| tree | 8bf2d874ec3e2a10045a57467b4c196b4723b133 /arch | |
| parent | 5a868c35e2dc2022f649336c2e64b79b8a04381f (diff) | |
| download | barebox-a9fe1f9be67408f21800a99cbd8c5399ee3297f0.tar.gz barebox-a9fe1f9be67408f21800a99cbd8c5399ee3297f0.tar.xz | |
VFxxx: Reconcile shared DDR DCD configuration with U-Boot
U-Boot was originally used as a source of DCD for VFxxx, so update our
settings against latest upstream (sha1:
b8aa55cb6414e512cce30bb7db3268eea934466d) to reconcile the
differences.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg | 1 | ||||
| -rw-r--r-- | arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-cr-default.imxcfg | 8 |
2 files changed, 3 insertions, 6 deletions
diff --git a/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg b/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg index 7bb7e8ac69..6445cbe9d1 100644 --- a/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg +++ b/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg @@ -9,7 +9,6 @@ dcdofs 0x400 #include <mach/flash-header/vf610-iomux-ddr-default.imxcfg> #include <mach/flash-header/vf610-ddr-cr-default.imxcfg> -wm 32 DDRMC_CR02 0x00000005 wm 32 DDRMC_CR12 0x00000506 wm 32 DDRMC_CR13 0x06040400 wm 32 DDRMC_CR14 0x1006040e diff --git a/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-cr-default.imxcfg b/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-cr-default.imxcfg index e64f4838e3..3563494cce 100644 --- a/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-cr-default.imxcfg +++ b/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-cr-default.imxcfg @@ -1,5 +1,5 @@ wm 32 DDRMC_CR00 DDRMC_CR00_DRAM_CLASS_DDR3 -wm 32 DDRMC_CR02 0x00000020 +wm 32 DDRMC_CR02 0x00000005 wm 32 DDRMC_CR10 0x00013880 wm 32 DDRMC_CR11 0x00030d40 wm 32 DDRMC_CR12 0x0000050c @@ -50,8 +50,6 @@ wm 32 DDRMC_CR102 0x00010100 wm 32 DDRMC_CR105 0x00000000 wm 32 DDRMC_CR106 0x00000004 wm 32 DDRMC_CR110 0x00040000 -wm 32 DDRMC_CR114 0x00000000 -wm 32 DDRMC_CR115 0x00000000 wm 32 DDRMC_CR117 0x00000000 wm 32 DDRMC_CR118 0x01010000 wm 32 DDRMC_CR120 0x02020000 @@ -69,7 +67,7 @@ wm 32 DDRMC_CR126 0x00000800 */ wm 32 DDRMC_CR132 0x00000506 wm 32 DDRMC_CR137 0x00020000 -wm 32 DDRMC_CR138 0x01000000 +wm 32 DDRMC_CR138 0x01000100 wm 32 DDRMC_CR139 0x04070303 wm 32 DDRMC_CR140 0x00000040 wm 32 DDRMC_CR143 0x06000080 @@ -80,6 +78,6 @@ wm 32 DDRMC_CR147 0x000f0000 wm 32 DDRMC_CR148 0x000f0000 wm 32 DDRMC_CR151 0x00000101 wm 32 DDRMC_CR154 0x682c4000 -wm 32 DDRMC_CR155 0x00000012 +wm 32 DDRMC_CR155 0x00000009 wm 32 DDRMC_CR158 0x00000006 wm 32 DDRMC_CR161 0x00010202
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