ARM: sync_caches_for_execution: don't flush disabled data cache

We unconditionally clean and then invalidate D-cache entries in
sync_caches_for_execution by calling arm_early_mmu_cache_flush().

The function afterwards takes care to invalidate the I-cache.

This misbehaves though when the D-Cache contains stale dirty
entries for currently executing code. Most boards avoid this
pitfall, because barebox_arm_entry calls
arm_early_mmu_cache_invalidate() and sync_caches_for_execution()
is only called afterwards. But for some boards,
relocate_to_current_adr() is called before barebox_arm_entry and
various board code works around this by calling
arm_early_mmu_cache_invalidate() first.

Make this unnecessary by not flushing the data cache when it's disabled
and instead only invalidate the I-Cache.

This fixes a hang observed on a serial-booted i.MX6Q rev 1.5
executing relocate_to_current_adr() -> sync_caches_for_execution()
from On-Chip SRAM.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20220901104136.171051-1-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

1 files changed, 6 insertions, 0 deletions

diff --git a/arch/arm/cpu/common.c b/arch/arm/cpu/common.c
index 8cfcc8f6ce..5ccacf2047 100644
--- a/arch/arm/cpu/common.c
+++ b/arch/arm/cpu/common.c
@@ -23,6 +23,12 @@
  */
 void sync_caches_for_execution(void)
 {
+	/* if caches are disabled, don't do data cache maintenance */
+	if (!(get_cr() & CR_C)) {
+		icache_invalidate();
+		return;
+	}
+
 	/*
 	 * Despite the name arm_early_mmu_cache_flush not only flushes the
 	 * data cache, but also invalidates the instruction cache.