diff options
| author | Uwe Kleine-König <u.kleine-koenig@pengutronix.de> | 2017-08-01 11:50:30 +0200 |
|---|---|---|
| committer | Lucas Stach <l.stach@pengutronix.de> | 2017-08-15 15:12:48 +0200 |
| commit | dd2e8bed52118102b5900ed827173ed76813319f (patch) | |
| tree | 8b45c406903b55d88b9a489038cb7af0eb10a014 /arch | |
| parent | d01954ef973a883fe8d51c610c1f89dc5bbc9f1e (diff) | |
| download | barebox-dd2e8bed52118102b5900ed827173ed76813319f.tar.gz barebox-dd2e8bed52118102b5900ed827173ed76813319f.tar.xz | |
ARM: imx: phyCORE i.MX7: use register defines in dcd table
This was done using scripts/regsubst.pl.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg | 94 |
1 files changed, 48 insertions, 46 deletions
diff --git a/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg b/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg index b1608dd9c7..6c256e8fc5 100644 --- a/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg +++ b/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg @@ -13,64 +13,66 @@ soc imx7 loadaddr 0x80000000 dcdofs 0x400 +#include <mach/imx7-ddr-regs.h> + wm 32 0x30340004 0x4F400005 /* Clear then set bit30 to ensure exit from DDR retention */ wm 32 0x30360388 0x40000000 wm 32 0x30360384 0x40000000 wm 32 0x30391000 0x00000002 -wm 32 0x307a0000 0x01040001 -wm 32 0x307a01a0 0x80400003 -wm 32 0x307a01a4 0x00100020 -wm 32 0x307a01a8 0x80100004 -wm 32 0x307a0064 0x00400046 -wm 32 0x307a0490 0x00000001 -wm 32 0x307a00d0 0x00020083 -wm 32 0x307a00d4 0x00690000 -wm 32 0x307a00dc 0x09300004 -wm 32 0x307a00e0 0x04080000 -wm 32 0x307a00e4 0x00100004 -wm 32 0x307a00f4 0x0000033f -wm 32 0x307a0100 0x09081109 -wm 32 0x307a0104 0x0007020d -wm 32 0x307a0108 0x03040407 -wm 32 0x307a010c 0x00002006 -wm 32 0x307a0110 0x04020205 -wm 32 0x307a0114 0x03030202 -wm 32 0x307a0120 0x00000803 -wm 32 0x307a0180 0x00800020 -wm 32 0x307a0184 0x02000100 -wm 32 0x307a0190 0x02098204 -wm 32 0x307a0194 0x00030303 -wm 32 0x307a0200 0x00000016 -wm 32 0x307a0204 0x00171717 -wm 32 0x307a0214 0x04040404 -wm 32 0x307a0218 0x0f040404 -wm 32 0x307a0240 0x06000604 -wm 32 0x307a0244 0x00000001 +wm 32 MX7_DDRC_MSTR 0x01040001 +wm 32 MX7_DDRC_DFIUPD0 0x80400003 +wm 32 MX7_DDRC_DFIUPD1 0x00100020 +wm 32 MX7_DDRC_DFIUPD2 0x80100004 +wm 32 MX7_DDRC_RFSHTMG 0x00400046 +wm 32 MX7_DDRC_MP_PCTRL_0 0x00000001 +wm 32 MX7_DDRC_INIT0 0x00020083 +wm 32 MX7_DDRC_INIT1 0x00690000 +wm 32 MX7_DDRC_INIT3 0x09300004 +wm 32 MX7_DDRC_INIT4 0x04080000 +wm 32 MX7_DDRC_INIT5 0x00100004 +wm 32 MX7_DDRC_RANKCTL 0x0000033f +wm 32 MX7_DDRC_DRAMTMG0 0x09081109 +wm 32 MX7_DDRC_DRAMTMG1 0x0007020d +wm 32 MX7_DDRC_DRAMTMG2 0x03040407 +wm 32 MX7_DDRC_DRAMTMG3 0x00002006 +wm 32 MX7_DDRC_DRAMTMG4 0x04020205 +wm 32 MX7_DDRC_DRAMTMG5 0x03030202 +wm 32 MX7_DDRC_DRAMTMG8 0x00000803 +wm 32 MX7_DDRC_ZQCTL0 0x00800020 +wm 32 MX7_DDRC_ZQCTL1 0x02000100 +wm 32 MX7_DDRC_DFITMG0 0x02098204 +wm 32 MX7_DDRC_DFITMG1 0x00030303 +wm 32 MX7_DDRC_ADDRMAP0 0x00000016 +wm 32 MX7_DDRC_ADDRMAP1 0x00171717 +wm 32 MX7_DDRC_ADDRMAP5 0x04040404 +wm 32 MX7_DDRC_ADDRMAP6 0x0f040404 +wm 32 MX7_DDRC_ODTCFG 0x06000604 +wm 32 MX7_DDRC_ODTMAP 0x00000001 wm 32 0x30391000 0x00000000 -wm 32 0x30790000 0x17420f40 -wm 32 0x30790004 0x10210100 -wm 32 0x30790010 0x00060807 -wm 32 0x307900b0 0x1010007e -wm 32 0x3079009c 0x00000d6e -wm 32 0x30790020 0x08080808 -wm 32 0x30790030 0x08080808 -wm 32 0x30790050 0x01000010 -wm 32 0x30790050 0x00000010 +wm 32 MX7_DDR_PHY_PHY_CON0 0x17420f40 +wm 32 MX7_DDR_PHY_PHY_CON1 0x10210100 +wm 32 MX7_DDR_PHY_PHY_CON4 0x00060807 +wm 32 MX7_DDR_PHY_MDLL_CON0 0x1010007e +wm 32 MX7_DDR_PHY_DRVDS_CON0 0x00000d6e +wm 32 MX7_DDR_PHY_OFFSET_RD_CON0 0x08080808 +wm 32 MX7_DDR_PHY_OFFSET_WR_CON0 0x08080808 +wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x01000010 +wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x00000010 -wm 32 0x307900c0 0x0e407304 -wm 32 0x307900c0 0x0e447304 -wm 32 0x307900c0 0x0e447306 +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304 +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304 +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447306 -check 32 while_any_bit_clear 0x307900c4 0x1 +check 32 while_any_bit_clear MX7_DDR_PHY_ZQ_CON1 0x1 -wm 32 0x307900c0 0x0e447304 -wm 32 0x307900c0 0x0e407304 +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304 +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304 wm 32 0x30384130 0x00000000 wm 32 0x30340020 0x00000178 wm 32 0x30384130 0x00000002 -wm 32 0x30790018 0x0000000f +wm 32 MX7_DDR_PHY_LP_CON0 0x0000000f -check 32 while_any_bit_clear 0x307a0004 0x1 +check 32 while_any_bit_clear MX7_DDRC_STAT 0x1 |