diff options
| author | Sascha Hauer <s.hauer@pengutronix.de> | 2018-11-05 13:59:29 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-11-06 09:39:22 +0100 |
| commit | edd34f73a78300277237c1ebb276cb6e01081ad2 (patch) | |
| tree | 66ee71583205f6a58a73f07fe512db8f799a2796 /arch | |
| parent | f3e537c20c3af5d37704640c15b6cb70140ba55e (diff) | |
| download | barebox-edd34f73a78300277237c1ebb276cb6e01081ad2.tar.gz barebox-edd34f73a78300277237c1ebb276cb6e01081ad2.tar.xz | |
ARM: at91rm9200ek: use plain readl/writel for pmc accesses
at91_pmc_write() needs a compile time base address, so rather use plain
read/writel.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boards/at91rm9200ek/lowlevel.c | 17 | ||||
| -rw-r--r-- | arch/arm/mach-at91/include/mach/at91rm9200.h | 1 |
2 files changed, 10 insertions, 8 deletions
diff --git a/arch/arm/boards/at91rm9200ek/lowlevel.c b/arch/arm/boards/at91rm9200ek/lowlevel.c index 3fb6ca3381..a5c9058552 100644 --- a/arch/arm/boards/at91rm9200ek/lowlevel.c +++ b/arch/arm/boards/at91rm9200ek/lowlevel.c @@ -26,23 +26,24 @@ void __naked __bare_init barebox_arm_reset_vector(void) u32 r; int i; void __iomem *mc = IOMEM(AT91RM9200_BASE_MC); + void __iomem *pmc = IOMEM(AT91RM9200_BASE_PMC); arm_cpu_lowlevel_init(); /* * PMC Check if the PLL is already initialized */ - r = at91_pmc_read(AT91_PMC_MCKR); + r = __raw_readl(pmc + AT91_PMC_MCKR); if (r & AT91_PMC_CSS) goto end; /* * Enable the Main Oscillator */ - at91_pmc_write(AT91_CKGR_MOR, CONFIG_SYS_MOR_VAL); + __raw_writel(CONFIG_SYS_MOR_VAL, pmc + AT91_CKGR_MOR); do { - r = at91_pmc_read(AT91_PMC_SR); + r = __raw_readl(pmc + AT91_PMC_SR); } while (!(r & AT91_PMC_MOSCS)); /* @@ -62,24 +63,24 @@ void __naked __bare_init barebox_arm_reset_vector(void) /* * PLLAR: x MHz for PCK */ - at91_pmc_write(AT91_CKGR_PLLAR, CONFIG_SYS_PLLAR_VAL); + __raw_writel(CONFIG_SYS_PLLAR_VAL, pmc + AT91_CKGR_PLLAR); do { - r = at91_pmc_read(AT91_PMC_SR); + r = __raw_readl(pmc + AT91_PMC_SR); } while (!(r & AT91_PMC_LOCKA)); /* * PCK/x = MCK Master Clock from SLOW */ - at91_pmc_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL1); + __raw_writel(CONFIG_SYS_MCKR2_VAL1, pmc + AT91_PMC_MCKR); /* * PCK/x = MCK Master Clock from PLLA */ - at91_pmc_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL2); + __raw_writel(CONFIG_SYS_MCKR2_VAL2, pmc + AT91_PMC_MCKR); do { - r = at91_pmc_read(AT91_PMC_SR); + r = __raw_readl(pmc + AT91_PMC_SR); } while (!(r & AT91_PMC_MCKRDY)); /* diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h index d06dfa7388..e2af3585af 100644 --- a/arch/arm/mach-at91/include/mach/at91rm9200.h +++ b/arch/arm/mach-at91/include/mach/at91rm9200.h @@ -84,6 +84,7 @@ #define AT91RM9200_BASE_PIOB 0xfffff600 /* PIO Controller B */ #define AT91RM9200_BASE_PIOC 0xfffff800 /* PIO Controller C */ #define AT91RM9200_BASE_PIOD 0xfffffa00 /* PIO Controller D */ +#define AT91RM9200_BASE_PMC 0xfffffc00 #define AT91RM9200_BASE_ST 0xfffffd00 /* System Timer */ #define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */ #define AT91RM9200_BASE_MC 0xffffff00 /* Memory Controllers */ |