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author | Antony Pavlov <antonynpavlov@gmail.com> | 2012-05-22 16:17:01 +0400 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2012-05-23 18:47:53 +0200 |
commit | f3d865e29c041eb4da38f5893dadf63aa7338337 (patch) | |
tree | 2c09248ce678ee88f3379ca3f91e76dd7b56d969 /arch | |
parent | e41b0717dc6594e8cf063b7023fde814f2ac97b4 (diff) | |
download | barebox-f3d865e29c041eb4da38f5893dadf63aa7338337.tar.gz barebox-f3d865e29c041eb4da38f5893dadf63aa7338337.tar.xz |
MIPS: cpuinfo: import CPU message from Linux 3.4
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/mips/lib/cpuinfo.c | 27 |
1 files changed, 25 insertions, 2 deletions
diff --git a/arch/mips/lib/cpuinfo.c b/arch/mips/lib/cpuinfo.c index fc8fb00f0f..c0bb87a5fe 100644 --- a/arch/mips/lib/cpuinfo.c +++ b/arch/mips/lib/cpuinfo.c @@ -23,11 +23,34 @@ #include <common.h> #include <command.h> #include <asm/mipsregs.h> +#include <asm/cpu-info.h> + +static char *way_string[] = { NULL, "direct mapped", "2-way", + "3-way", "4-way", "5-way", "6-way", "7-way", "8-way" +}; static int do_cpuinfo(int argc, char *argv[]) { - printf("CP0_PRID = 0x%08x\n", read_c0_prid()); - printf("CP0_CONFIG = 0x%08x\n", read_c0_config()); + unsigned int icache_size, dcache_size; + struct cpuinfo_mips *c = ¤t_cpu_data; + + printk(KERN_INFO "CPU revision is: %08x (%s)\n", + current_cpu_data.processor_id, __cpu_name); + + icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; + dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; + + printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", + icache_size >> 10, + c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT", + way_string[c->icache.ways], c->icache.linesz); + + printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n", + dcache_size >> 10, way_string[c->dcache.ways], + (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT", + (c->dcache.flags & MIPS_CACHE_ALIASES) ? + "cache aliases" : "no aliases", + c->dcache.linesz); return 0; } |