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authorSascha Hauer <s.hauer@pengutronix.de>2020-03-18 08:48:16 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2020-03-18 08:48:16 +0100
commitfcad6e3394943e32bc9e08d971f2c6511a99a151 (patch)
treef8f4ad6996ef81492d49c36273ef78aac75bd781 /arch
parent394b88e6872c607e5317cf57c61c641288555311 (diff)
parente6e12e9368f730d5e50c9495c2332abe2ad6abf0 (diff)
downloadbarebox-fcad6e3394943e32bc9e08d971f2c6511a99a151.tar.gz
Merge branch 'for-next/imx'
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boards/Makefile1
-rw-r--r--arch/arm/boards/freescale-mx7-sabresd/lowlevel.c12
-rw-r--r--arch/arm/boards/nxp-imx8mm-evk/Makefile2
-rw-r--r--arch/arm/boards/nxp-imx8mm-evk/board.c81
-rw-r--r--arch/arm/boards/nxp-imx8mm-evk/flash-header-imx8mm-evk.imxcfg5
-rw-r--r--arch/arm/boards/nxp-imx8mm-evk/lowlevel.c184
-rw-r--r--arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c1976
-rw-r--r--arch/arm/boards/nxp-imx8mq-evk/ddr.h9
-rw-r--r--arch/arm/boards/nxp-imx8mq-evk/lowlevel.c25
-rw-r--r--arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-512mb.imxcfg9
-rw-r--r--arch/arm/boards/phytec-som-imx6/lowlevel.c1
-rw-r--r--arch/arm/boards/phytec-som-imx8mq/ddr.h7
-rw-r--r--arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c1
-rw-r--r--arch/arm/boards/phytec-som-imx8mq/lowlevel.c25
-rw-r--r--arch/arm/boards/zii-imx7d-dev/lowlevel.c12
-rw-r--r--arch/arm/boards/zii-imx8mq-dev/ddr.h9
-rw-r--r--arch/arm/boards/zii-imx8mq-dev/lowlevel.c25
-rw-r--r--arch/arm/configs/imx_v8_defconfig18
-rw-r--r--arch/arm/dts/Makefile1
-rw-r--r--arch/arm/dts/imx51-genesi-efika-sb.dts6
-rw-r--r--arch/arm/dts/imx53-guf-vincell-lt.dts2
-rwxr-xr-xarch/arm/dts/imx6dl-advantech-rom-7421.dts12
-rw-r--r--arch/arm/dts/imx6dl-eltec-hipercam.dts4
-rw-r--r--arch/arm/dts/imx6q-guf-santaro.dts4
-rw-r--r--arch/arm/dts/imx6qdl-cm-fx6.dtsi2
-rw-r--r--arch/arm/dts/imx6qdl-hummingboard2.dtsi2
-rw-r--r--arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi10
-rw-r--r--arch/arm/dts/imx6qdl-tqma6x.dtsi2
-rw-r--r--arch/arm/dts/imx6qdl-tx6x.dtsi2
-rw-r--r--arch/arm/dts/imx7d-phycore-som.dtsi2
-rw-r--r--arch/arm/dts/imx8mm-evk.dts62
-rw-r--r--arch/arm/dts/vf610-zii-scu4-aib.dts8
-rw-r--r--arch/arm/mach-imx/Kconfig21
-rw-r--r--arch/arm/mach-imx/Makefile4
-rw-r--r--arch/arm/mach-imx/atf.c26
-rw-r--r--arch/arm/mach-imx/boot.c42
-rw-r--r--arch/arm/mach-imx/cpu_init.c14
-rw-r--r--arch/arm/mach-imx/esdctl.c30
-rw-r--r--arch/arm/mach-imx/imx-bbu-internal.c4
-rw-r--r--arch/arm/mach-imx/imx.c4
-rw-r--r--arch/arm/mach-imx/imx8-ddrc.c91
-rw-r--r--arch/arm/mach-imx/imx8m.c279
-rw-r--r--arch/arm/mach-imx/imx8mq.c111
-rw-r--r--arch/arm/mach-imx/include/mach/atf.h9
-rw-r--r--arch/arm/mach-imx/include/mach/debug_ll.h4
-rw-r--r--arch/arm/mach-imx/include/mach/esdctl.h1
-rw-r--r--arch/arm/mach-imx/include/mach/generic.h22
-rw-r--r--arch/arm/mach-imx/include/mach/imx7-ccm-regs.h45
-rw-r--r--arch/arm/mach-imx/include/mach/imx8-ccm-regs.h15
-rw-r--r--arch/arm/mach-imx/include/mach/imx8-ddrc.h66
-rw-r--r--arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h57
-rw-r--r--arch/arm/mach-imx/include/mach/imx8m-regs.h37
-rw-r--r--arch/arm/mach-imx/include/mach/imx8mm-regs.h46
-rw-r--r--arch/arm/mach-imx/include/mach/imx8mq-regs.h2
-rw-r--r--arch/arm/mach-imx/include/mach/imx8mq.h13
-rw-r--r--arch/arm/mach-imx/include/mach/imx_cpu_types.h1
-rw-r--r--arch/arm/mach-imx/include/mach/iomux-mx7.h4
-rw-r--r--arch/arm/mach-imx/include/mach/iomux-mx8m.h27
-rw-r--r--arch/arm/mach-imx/include/mach/iomux-mx8mm.h701
-rw-r--r--arch/arm/mach-imx/include/mach/iomux-mx8mq.h (renamed from arch/arm/mach-imx/include/mach/iomux-mx8.h)24
-rw-r--r--arch/arm/mach-imx/include/mach/xload.h2
61 files changed, 3753 insertions, 470 deletions
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index edc600b..9fe458e 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -84,6 +84,7 @@ obj-$(CONFIG_MACH_NVIDIA_BEAVER) += nvidia-beaver/
obj-$(CONFIG_MACH_NVIDIA_JETSON) += nvidia-jetson-tk1/
obj-$(CONFIG_MACH_NXP_IMX6ULL_EVK) += nxp-imx6ull-evk/
obj-$(CONFIG_MACH_NXP_IMX8MQ_EVK) += nxp-imx8mq-evk/
+obj-$(CONFIG_MACH_NXP_IMX8MM_EVK) += nxp-imx8mm-evk/
obj-$(CONFIG_MACH_OMAP343xSDP) += omap343xdsp/
obj-$(CONFIG_MACH_OMAP3EVM) += omap3evm/
obj-$(CONFIG_MACH_PANDA) += panda/
diff --git a/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c b/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c
index f718ea7..8db46ca 100644
--- a/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c
+++ b/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c
@@ -15,17 +15,9 @@ extern char __dtb_imx7d_sdb_start[];
static inline void setup_uart(void)
{
- void __iomem *iomux = IOMEM(MX7_IOMUXC_BASE_ADDR);
- void __iomem *ccm = IOMEM(MX7_CCM_BASE_ADDR);
+ imx7_early_setup_uart_clock();
- writel(CCM_CCGR_SETTINGn_NEEDED(0),
- ccm + CCM_CCGRn_CLR(CCM_CCGR_UART1));
- writel(CCM_TARGET_ROOTn_ENABLE | UART1_CLK_ROOT__OSC_24M,
- ccm + CCM_TARGET_ROOTn(UART1_CLK_ROOT));
- writel(CCM_CCGR_SETTINGn_NEEDED(0),
- ccm + CCM_CCGRn_SET(CCM_CCGR_UART1));
-
- mx7_setup_pad(iomux, MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX);
+ imx7_setup_pad(MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX);
imx7_uart_setup_ll();
diff --git a/arch/arm/boards/nxp-imx8mm-evk/Makefile b/arch/arm/boards/nxp-imx8mm-evk/Makefile
new file mode 100644
index 0000000..4d0d989
--- /dev/null
+++ b/arch/arm/boards/nxp-imx8mm-evk/Makefile
@@ -0,0 +1,2 @@
+obj-y += board.o
+lwl-y += lowlevel.o lpddr4-timing.o
diff --git a/arch/arm/boards/nxp-imx8mm-evk/board.c b/arch/arm/boards/nxp-imx8mm-evk/board.c
new file mode 100644
index 0000000..5958227
--- /dev/null
+++ b/arch/arm/boards/nxp-imx8mm-evk/board.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2018 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation.
+ *
+ */
+
+#include <asm/memory.h>
+#include <bootsource.h>
+#include <common.h>
+#include <init.h>
+#include <linux/phy.h>
+#include <linux/sizes.h>
+#include <mach/bbu.h>
+
+#include <envfs.h>
+
+#define PHY_ID_AR8031 0x004dd074
+#define AR_PHY_ID_MASK 0xffffffff
+
+static int ar8031_phy_fixup(struct phy_device *phydev)
+{
+ /*
+ * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
+ * Phy control debug reg 0
+ */
+ phy_write(phydev, 0x1d, 0x1f);
+ phy_write(phydev, 0x1e, 0x8);
+
+ /* rgmii tx clock delay enable */
+ phy_write(phydev, 0x1d, 0x05);
+ phy_write(phydev, 0x1e, 0x100);
+
+ return 0;
+}
+
+static int nxp_imx8mm_evk_init(void)
+{
+ int emmc_bbu_flag = 0;
+ int emmc_sd_flag = 0;
+
+ if (!of_machine_is_compatible("fsl,imx8mm-evk"))
+ return 0;
+
+ barebox_set_hostname("imx8mm-evk");
+
+ if (bootsource_get() == BOOTSOURCE_MMC) {
+ if (bootsource_get_instance() == 2) {
+ of_device_enable_path("/chosen/environment-emmc");
+ emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+ } else {
+ of_device_enable_path("/chosen/environment-sd");
+ emmc_sd_flag = BBU_HANDLER_FLAG_DEFAULT;
+ }
+ } else {
+ of_device_enable_path("/chosen/environment-emmc");
+ emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+ }
+
+ imx8mq_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox",
+ emmc_sd_flag);
+ imx8mq_bbu_internal_mmc_register_handler("eMMC", "/dev/mmc2",
+ emmc_bbu_flag);
+
+ phy_register_fixup_for_uid(PHY_ID_AR8031, AR_PHY_ID_MASK,
+ ar8031_phy_fixup);
+ return 0;
+}
+device_initcall(nxp_imx8mm_evk_init);
diff --git a/arch/arm/boards/nxp-imx8mm-evk/flash-header-imx8mm-evk.imxcfg b/arch/arm/boards/nxp-imx8mm-evk/flash-header-imx8mm-evk.imxcfg
new file mode 100644
index 0000000..727439d
--- /dev/null
+++ b/arch/arm/boards/nxp-imx8mm-evk/flash-header-imx8mm-evk.imxcfg
@@ -0,0 +1,5 @@
+soc imx8mm
+
+loadaddr 0x007e1000
+max_load_size 0x3f000
+dcdofs 0x400
diff --git a/arch/arm/boards/nxp-imx8mm-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mm-evk/lowlevel.c
new file mode 100644
index 0000000..cd1f7d1
--- /dev/null
+++ b/arch/arm/boards/nxp-imx8mm-evk/lowlevel.c
@@ -0,0 +1,184 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <io.h>
+#include <common.h>
+#include <debug_ll.h>
+#include <firmware.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/sections.h>
+#include <asm/barebox-arm.h>
+#include <asm/barebox-arm-head.h>
+#include <i2c/i2c-early.h>
+#include <linux/sizes.h>
+#include <mach/atf.h>
+#include <mach/xload.h>
+#include <mach/esdctl.h>
+#include <mach/generic.h>
+#include <mach/imx8mm-regs.h>
+#include <mach/iomux-mx8mm.h>
+#include <mach/imx8m-ccm-regs.h>
+#include <mfd/bd71837.h>
+#include <soc/imx8m/ddr.h>
+#include <soc/fsl/fsl_udc.h>
+
+extern char __dtb_imx8mm_evk_start[];
+
+#define UART_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DSE_3P3V_45_OHM)
+
+static void setup_uart(void)
+{
+ imx8m_early_setup_uart_clock();
+
+ imx8mm_setup_pad(IMX8MM_PAD_UART2_TXD_UART2_TX | UART_PAD_CTRL);
+
+ imx8m_uart_setup_ll();
+
+ putc_ll('>');
+}
+
+static void pmic_reg_write(void *i2c, int reg, uint8_t val)
+{
+ int ret;
+ u8 buf[32];
+ struct i2c_msg msgs[] = {
+ {
+ .addr = 0x4b,
+ .buf = buf,
+ },
+ };
+
+ buf[0] = reg;
+ buf[1] = val;
+
+ msgs[0].len = 2;
+
+ ret = i2c_fsl_xfer(i2c, msgs, ARRAY_SIZE(msgs));
+ if (ret != 1)
+ pr_err("Failed to write to pmic\n");
+}
+
+static int power_init_board(void)
+{
+ void *i2c;
+
+ imx8mm_setup_pad(IMX8MM_PAD_I2C1_SCL_I2C1_SCL);
+ imx8mm_setup_pad(IMX8MM_PAD_I2C1_SDA_I2C1_SDA);
+
+ imx8mm_early_clock_init();
+ imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1);
+
+ i2c = imx8m_i2c_early_init(IOMEM(MX8MQ_I2C1_BASE_ADDR));
+
+ /* decrease RESET key long push time from the default 10s to 10ms */
+ pmic_reg_write(i2c, BD718XX_PWRONCONFIG1, 0x0);
+
+ /* unlock the PMIC regs */
+ pmic_reg_write(i2c, BD718XX_REGLOCK, 0x1);
+
+ /* increase VDD_SOC to typical value 0.85v before first DRAM access */
+ pmic_reg_write(i2c, BD718XX_BUCK1_VOLT_RUN, 0x0f);
+
+ /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
+ pmic_reg_write(i2c, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
+
+ /* lock the PMIC regs */
+ pmic_reg_write(i2c, BD718XX_REGLOCK, 0x11);
+
+ return 0;
+}
+
+extern struct dram_timing_info imx8mm_evk_dram_timing;
+
+static void start_atf(void)
+{
+ size_t bl31_size;
+ const u8 *bl31;
+ enum bootsource src;
+ int instance;
+
+ /*
+ * If we are in EL3 we are running for the first time and need to
+ * initialize the DRAM and run TF-A (BL31). The TF-A will then jump
+ * to DRAM in EL2.
+ */
+ if (current_el() != 3)
+ return;
+
+ power_init_board();
+ imx8mm_ddr_init(&imx8mm_evk_dram_timing);
+
+ imx8mm_get_boot_source(&src, &instance);
+ switch (src) {
+ case BOOTSOURCE_MMC:
+ imx8m_esdhc_load_image(instance, false);
+ break;
+ case BOOTSOURCE_SERIAL:
+ imx8mm_barebox_load_usb((void *)MX8M_ATF_BL33_BASE_ADDR);
+ break;
+ default:
+ printf("Unhandled bootsource BOOTSOURCE_%d\n", src);
+ hang();
+ }
+
+ /*
+ * On completion the TF-A will jump to MX8M_ATF_BL33_BASE_ADDR
+ * in EL2. Copy the image there, but replace the PBL part of
+ * that image with ourselves. On a high assurance boot only the
+ * currently running code is validated and contains the checksum
+ * for the piggy data, so we need to ensure that we are running
+ * the same code in DRAM.
+ */
+ memcpy((void *)MX8M_ATF_BL33_BASE_ADDR,
+ __image_start, barebox_pbl_size);
+
+ get_builtin_firmware(imx8mm_bl31_bin, &bl31, &bl31_size);
+
+ imx8mm_atf_load_bl31(bl31, bl31_size);
+
+ /* not reached */
+}
+
+/*
+ * Power-on execution flow of start_nxp_imx8mm_evk() might not be
+ * obvious for a very first read, so here's, hopefully helpful,
+ * summary:
+ *
+ * 1. MaskROM uploads PBL into OCRAM and that's where this function is
+ * executed for the first time. At entry the exception level is EL3.
+ *
+ * 2. DDR is initialized and the image is loaded from storage into DRAM. The PBL
+ * part is copied from OCRAM to the TF-A return address in DRAM.
+ *
+ * 3. TF-A is executed and exits into the PBL code in DRAM. TF-A has taken us
+ * from EL3 to EL2.
+ *
+ * 4. Standard barebox boot flow continues
+ */
+static __noreturn noinline void nxp_imx8mm_evk_start(void)
+{
+ if (IS_ENABLED(CONFIG_DEBUG_LL))
+ setup_uart();
+
+ start_atf();
+
+ /*
+ * Standard entry we hit once we initialized both DDR and ATF
+ */
+ imx8mm_barebox_entry(__dtb_imx8mm_evk_start);
+}
+
+ENTRY_FUNCTION(start_nxp_imx8mm_evk, r0, r1, r2)
+{
+ void __iomem *ccm = IOMEM(MX8M_CCM_BASE_ADDR);
+
+ writel(IMX8M_CCM_CCGR_SETTINGn_NEEDED(0),
+ ccm + IMX8M_CCM_CCGRn_SET(IMX8M_CCM_CCGR_SCTR));
+
+ imx8mm_cpu_lowlevel_init();
+
+ relocate_to_current_adr();
+ setup_c();
+
+ nxp_imx8mm_evk_start();
+}
diff --git a/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c b/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c
new file mode 100644
index 0000000..b164bde
--- /dev/null
+++ b/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c
@@ -0,0 +1,1976 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <soc/imx8m/ddr.h>
+#include <soc/imx8m/lpddr4_define.h>
+
+static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
+ /* Start to config, default 3200mbps */
+ { DDRC_DBG1(0), 0x00000001 },
+ { DDRC_PWRCTL(0), 0x00000001 },
+ { DDRC_MSTR(0), 0xa1080020 },
+ { DDRC_RFSHTMG(0), 0x005b00d2 },
+ { DDRC_INIT0(0), 0xC003061B },
+ { DDRC_INIT1(0), 0x009D0000 },
+ { DDRC_INIT3(0), 0x00D4002D },
+ { DDRC_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
+ { DDRC_INIT6(0), 0x0066004a },
+ { DDRC_INIT7(0), 0x0006004a },
+
+ { DDRC_DRAMTMG0(0), 0x1A201B22 },
+ { DDRC_DRAMTMG1(0), 0x00060633 },
+ { DDRC_DRAMTMG3(0), 0x00C0C000 },
+ { DDRC_DRAMTMG4(0), 0x0F04080F },
+ { DDRC_DRAMTMG5(0), 0x02040C0C },
+ { DDRC_DRAMTMG6(0), 0x01010007 },
+ { DDRC_DRAMTMG7(0), 0x00000401 },
+ { DDRC_DRAMTMG12(0), 0x00020600 },
+ { DDRC_DRAMTMG13(0), 0x0C100002 },
+ { DDRC_DRAMTMG14(0), 0x000000E6 },
+ { DDRC_DRAMTMG17(0), 0x00A00050 },
+
+ { DDRC_ZQCTL0(0), 0x03200018 },
+ { DDRC_ZQCTL1(0), 0x028061A8 },
+ { DDRC_ZQCTL2(0), 0x00000000 },
+
+ { DDRC_DFITMG0(0), 0x0497820A },
+ { DDRC_DFITMG2(0), 0x0000170A },
+ { DDRC_DRAMTMG2(0), 0x070E171a },
+ { DDRC_DBICTL(0), 0x00000001 },
+
+ { DDRC_DFITMG1(0), 0x00080303 },
+ { DDRC_DFIUPD0(0), 0xE0400018 },
+ { DDRC_DFIUPD1(0), 0x00DF00E4 },
+ { DDRC_DFIUPD2(0), 0x80000000 },
+ { DDRC_DFIMISC(0), 0x00000011 },
+
+ { DDRC_DFIPHYMSTR(0), 0x00000000 },
+ { DDRC_RANKCTL(0), 0x00000c99 },
+
+ /* address mapping */
+ { DDRC_ADDRMAP0(0), 0x0000001f },
+ { DDRC_ADDRMAP1(0), 0x00080808 },
+ { DDRC_ADDRMAP2(0), 0x00000000 },
+ { DDRC_ADDRMAP3(0), 0x00000000 },
+ { DDRC_ADDRMAP4(0), 0x00001f1f },
+ { DDRC_ADDRMAP5(0), 0x07070707 },
+ { DDRC_ADDRMAP6(0), 0x07070707 },
+ { DDRC_ADDRMAP7(0), 0x00000f0f },
+
+ /* performance setting */
+ { DDRC_SCHED(0), 0x29001701 },
+ { DDRC_SCHED1(0), 0x0000002c },
+ { DDRC_PERFHPR1(0), 0x04000030 },
+ { DDRC_PERFLPR1(0), 0x900093e7 },
+ { DDRC_PERFWR1(0), 0x20005574 },
+ { DDRC_PCCFG(0), 0x00000111 },
+ { DDRC_PCFGW_0(0), 0x000072ff },
+ { DDRC_PCFGQOS0_0(0), 0x02100e07 },
+ { DDRC_PCFGQOS1_0(0), 0x00620096 },
+ { DDRC_PCFGWQOS0_0(0), 0x01100e07 },
+ { DDRC_PCFGWQOS1_0(0), 0x00c8012c },
+
+ /* frequency P1&P2 */
+ /* Frequency 1: 400mbps */
+ { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
+ { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
+ { DDRC_FREQ1_DRAMTMG2(0), 0x0203090c },
+ { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 },
+ { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 },
+ { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
+ { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 },
+ { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e },
+ { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 },
+ { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
+ { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b },
+ { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 },
+ { DDRC_FREQ1_DFITMG0(0), 0x03818200 },
+ { DDRC_FREQ1_DFITMG2(0), 0x00000000 },
+ { DDRC_FREQ1_RFSHTMG(0), 0x000C001c },
+ { DDRC_FREQ1_INIT3(0), 0x00840000 },
+ { DDRC_FREQ1_INIT4(0), 0x00310000 },
+ { DDRC_FREQ1_INIT6(0), 0x0066004a },
+ { DDRC_FREQ1_INIT7(0), 0x0006004a },
+
+ /* Frequency 2: 100mbps */
+ { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c },
+ { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 },
+ { DDRC_FREQ2_DRAMTMG2(0), 0x0203090c },
+ { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 },
+ { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 },
+ { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 },
+ { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 },
+ { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e },
+ { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 },
+ { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b },
+ { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 },
+ { DDRC_FREQ2_DFITMG0(0), 0x03818200 },
+ { DDRC_FREQ2_DFITMG2(0), 0x00000000 },
+ { DDRC_FREQ2_RFSHTMG(0), 0x0003800c },
+ { DDRC_FREQ2_RFSHTMG(0), 0x00030007 },
+ { DDRC_FREQ2_INIT3(0), 0x00840000 },
+ { DDRC_FREQ2_INIT4(0), 0x00310008 },
+ { DDRC_FREQ2_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
+ { DDRC_FREQ2_INIT6(0), 0x0066004a },
+ { DDRC_FREQ2_INIT7(0), 0x0006004a },
+
+ /* boot start point */
+ { DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x1205f, 0x1ff },
+ { 0x1215f, 0x1ff },
+ { 0x1305f, 0x1ff },
+ { 0x1315f, 0x1ff },
+
+ { 0x11005f, 0x1ff },
+ { 0x11015f, 0x1ff },
+ { 0x11105f, 0x1ff },
+ { 0x11115f, 0x1ff },
+ { 0x11205f, 0x1ff },
+ { 0x11215f, 0x1ff },
+ { 0x11305f, 0x1ff },
+ { 0x11315f, 0x1ff },
+
+ { 0x21005f, 0x1ff },
+ { 0x21015f, 0x1ff },
+ { 0x21105f, 0x1ff },
+ { 0x21115f, 0x1ff },
+ { 0x21205f, 0x1ff },
+ { 0x21215f, 0x1ff },
+ { 0x21305f, 0x1ff },
+ { 0x21315f, 0x1ff },
+
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+
+ { 0x200c5, 0x19 },
+ { 0x1200c5, 0x7 },
+ { 0x2200c5, 0x7 },
+
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x2 },
+ { 0x22002e, 0x2 },
+
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+
+ { 0x20024, 0xab },
+ { 0x2003a, 0x0 },
+
+ { 0x120024, 0xab },
+ { 0x2003a, 0x0 },
+
+ { 0x220024, 0xab },
+ { 0x2003a, 0x0 },
+
+ { 0x20056, 0x3 },
+ { 0x120056, 0xa },
+ { 0x220056, 0xa },
+
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x1204d, 0xe00 },
+ { 0x1214d, 0xe00 },
+ { 0x1304d, 0xe00 },
+ { 0x1314d, 0xe00 },
+
+ { 0x11004d, 0xe00 },
+ { 0x11014d, 0xe00 },
+ { 0x11104d, 0xe00 },
+ { 0x11114d, 0xe00 },
+ { 0x11204d, 0xe00 },
+ { 0x11214d, 0xe00 },
+ { 0x11304d, 0xe00 },
+ { 0x11314d, 0xe00 },
+
+ { 0x21004d, 0xe00 },
+ { 0x21014d, 0xe00 },
+ { 0x21104d, 0xe00 },
+ { 0x21114d, 0xe00 },
+ { 0x21204d, 0xe00 },
+ { 0x21214d, 0xe00 },
+ { 0x21304d, 0xe00 },
+ { 0x21314d, 0xe00 },
+
+ { 0x10049, 0xfbe },
+ { 0x10149, 0xfbe },
+ { 0x11049, 0xfbe },
+ { 0x11149, 0xfbe },
+ { 0x12049, 0xfbe },
+ { 0x12149, 0xfbe },
+ { 0x13049, 0xfbe },
+ { 0x13149, 0xfbe },
+
+ { 0x110049, 0xfbe },
+ { 0x110149, 0xfbe },
+ { 0x111049, 0xfbe },
+ { 0x111149, 0xfbe },
+ { 0x112049, 0xfbe },
+ { 0x112149, 0xfbe },
+ { 0x113049, 0xfbe },
+ { 0x113149, 0xfbe },
+
+ { 0x210049, 0xfbe },
+ { 0x210149, 0xfbe },
+ { 0x211049, 0xfbe },
+ { 0x211149, 0xfbe },
+ { 0x212049, 0xfbe },
+ { 0x212149, 0xfbe },
+ { 0x213049, 0xfbe },
+ { 0x213149, 0xfbe },
+
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+
+ { 0x20018, 0x3 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x2ee },
+ { 0x120008, 0x64 },
+ { 0x220008, 0x19 },
+ { 0x20088, 0x9 },
+
+ { 0x200b2, 0x1d4 },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x12043, 0x5a1 },
+ { 0x12143, 0x5a1 },
+ { 0x13043, 0x5a1 },
+ { 0x13143, 0x5a1 },
+
+ { 0x1200b2, 0xdc },
+ { 0x110043, 0x5a1 },
+ { 0x110143, 0x5a1 },
+ { 0x111043, 0x5a1 },
+ { 0x111143, 0x5a1 },
+ { 0x112043, 0x5a1 },
+ { 0x112143, 0x5a1 },
+ { 0x113043, 0x5a1 },
+ { 0x113143, 0x5a1 },
+
+ { 0x2200b2, 0xdc },
+ { 0x210043, 0x5a1 },
+ { 0x210143, 0x5a1 },
+ { 0x211043, 0x5a1 },
+ { 0x211143, 0x5a1 },
+ { 0x212043, 0x5a1 },
+ { 0x212143, 0x5a1 },
+ { 0x213043, 0x5a1 },
+ { 0x213143, 0x5a1 },
+
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x2200fa, 0x1 },
+
+ { 0x20019, 0x1 },
+ { 0x120019, 0x1 },
+ { 0x220019, 0x1 },
+
+ { 0x200f0, 0x660 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5665 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+
+ { 0x20025, 0x0 },
+ { 0x2002d, LPDDR4_PHY_DMIPinPresent },
+ { 0x12002d, LPDDR4_PHY_DMIPinPresent },
+ { 0x22002d, LPDDR4_PHY_DMIPinPresent },
+ { 0x200c7, 0x21 },
+ { 0x200ca, 0x24 },
+ { 0x1200c7, 0x21 },
+ { 0x1200ca, 0x24 },
+ { 0x2200c7, 0x21 },
+ { 0x2200ca, 0x24 },
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0 },
+ { 0x1200b2, 0x0 },
+ { 0x2200b2, 0x0 },
+ { 0x200cb, 0x0 },
+ { 0x10043, 0x0 },
+ { 0x110043, 0x0 },
+ { 0x210043, 0x0 },
+ { 0x10143, 0x0 },
+ { 0x110143, 0x0 },
+ { 0x210143, 0x0 },
+ { 0x11043, 0x0 },
+ { 0x111043, 0x0 },
+ { 0x211043, 0x0 },
+ { 0x11143, 0x0 },
+ { 0x111143, 0x0 },
+ { 0x211143, 0x0 },
+ { 0x12043, 0x0 },
+ { 0x112043, 0x0 },
+ { 0x212043, 0x0 },
+ { 0x12143, 0x0 },
+ { 0x112143, 0x0 },
+ { 0x212143, 0x0 },
+ { 0x13043, 0x0 },
+ { 0x113043, 0x0 },
+ { 0x213043, 0x0 },
+ { 0x13143, 0x0 },
+ { 0x113143, 0x0 },
+ { 0x213143, 0x0 },
+ { 0x80, 0x0 },
+ { 0x100080, 0x0 },
+ { 0x200080, 0x0 },
+ { 0x1080, 0x0 },
+ { 0x101080, 0x0 },
+ { 0x201080, 0x0 },
+ { 0x2080, 0x0 },
+ { 0x102080, 0x0 },
+ { 0x202080, 0x0 },
+ { 0x3080, 0x0 },
+ { 0x103080, 0x0 },
+ { 0x203080, 0x0 },
+ { 0x4080, 0x0 },
+ { 0x104080, 0x0 },
+ { 0x204080, 0x0 },
+ { 0x5080, 0x0 },
+ { 0x105080, 0x0 },
+ { 0x205080, 0x0 },
+ { 0x6080, 0x0 },
+ { 0x106080, 0x0 },
+ { 0x206080, 0x0 },
+ { 0x7080, 0x0 },
+ { 0x107080, 0x0 },
+ { 0x207080, 0x0 },
+ { 0x8080, 0x0 },
+ { 0x108080, 0x0 },
+ { 0x208080, 0x0 },
+ { 0x9080, 0x0 },
+ { 0x109080, 0x0 },
+ { 0x209080, 0x0 },
+ { 0x10080, 0x0 },
+ { 0x110080, 0x0 },
+ { 0x210080, 0x0 },
+ { 0x10180, 0x0 },
+ { 0x110180, 0x0 },
+ { 0x210180, 0x0 },
+ { 0x11080, 0x0 },
+ { 0x111080, 0x0 },
+ { 0x211080, 0x0 },
+ { 0x11180, 0x0 },
+ { 0x111180, 0x0 },
+ { 0x211180, 0x0 },
+ { 0x12080, 0x0 },
+ { 0x112080, 0x0 },
+ { 0x212080, 0x0 },
+ { 0x12180, 0x0 },
+ { 0x112180, 0x0 },
+ { 0x212180, 0x0 },
+ { 0x13080, 0x0 },
+ { 0x113080, 0x0 },
+ { 0x213080, 0x0 },
+ { 0x13180, 0x0 },
+ { 0x113180, 0x0 },
+ { 0x213180, 0x0 },
+ { 0x10081, 0x0 },
+ { 0x110081, 0x0 },
+ { 0x210081, 0x0 },
+ { 0x10181, 0x0 },
+ { 0x110181, 0x0 },
+ { 0x210181, 0x0 },
+ { 0x11081, 0x0 },
+ { 0x111081, 0x0 },
+ { 0x211081, 0x0 },
+ { 0x11181, 0x0 },
+ { 0x111181, 0x0 },
+ { 0x211181, 0x0 },
+ { 0x12081, 0x0 },
+ { 0x112081, 0x0 },
+ { 0x212081, 0x0 },
+ { 0x12181, 0x0 },
+ { 0x112181, 0x0 },
+ { 0x212181, 0x0 },
+ { 0x13081, 0x0 },
+ { 0x113081, 0x0 },
+ { 0x213081, 0x0 },
+ { 0x13181, 0x0 },
+ { 0x113181, 0x0 },
+ { 0x213181, 0x0 },
+ { 0x100d0, 0x0 },
+ { 0x1100d0, 0x0 },
+ { 0x2100d0, 0x0 },
+ { 0x101d0, 0x0 },
+ { 0x1101d0, 0x0 },
+ { 0x2101d0, 0x0 },
+ { 0x110d0, 0x0 },
+ { 0x1110d0, 0x0 },
+ { 0x2110d0, 0x0 },
+ { 0x111d0, 0x0 },
+ { 0x1111d0, 0x0 },
+ { 0x2111d0, 0x0 },
+ { 0x120d0, 0x0 },
+ { 0x1120d0, 0x0 },
+ { 0x2120d0, 0x0 },
+ { 0x121d0, 0x0 },
+ { 0x1121d0, 0x0 },
+ { 0x2121d0, 0x0 },
+ { 0x130d0, 0x0 },
+ { 0x1130d0, 0x0 },
+ { 0x2130d0, 0x0 },
+ { 0x131d0, 0x0 },
+ { 0x1131d0, 0x0 },
+ { 0x2131d0, 0x0 },
+ { 0x100d1, 0x0 },
+ { 0x1100d1, 0x0 },
+ { 0x2100d1, 0x0 },
+ { 0x101d1, 0x0 },
+ { 0x1101d1, 0x0 },
+ { 0x2101d1, 0x0 },
+ { 0x110d1, 0x0 },
+ { 0x1110d1, 0x0 },
+ { 0x2110d1, 0x0 },
+ { 0x111d1, 0x0 },
+ { 0x1111d1, 0x0 },
+ { 0x2111d1, 0x0 },
+ { 0x120d1, 0x0 },
+ { 0x1120d1, 0x0 },
+ { 0x2120d1, 0x0 },
+ { 0x121d1, 0x0 },
+ { 0x1121d1, 0x0 },
+ { 0x2121d1, 0x0 },
+ { 0x130d1, 0x0 },
+ { 0x1130d1, 0x0 },
+ { 0x2130d1, 0x0 },
+ { 0x131d1, 0x0 },
+ { 0x1131d1, 0x0 },
+ { 0x2131d1, 0x0 },
+ { 0x10068, 0x0 },
+ { 0x10168, 0x0 },
+ { 0x10268, 0x0 },
+ { 0x10368, 0x0 },
+ { 0x10468, 0x0 },
+ { 0x10568, 0x0 },
+ { 0x10668, 0x0 },
+ { 0x10768, 0x0 },
+ { 0x10868, 0x0 },
+ { 0x11068, 0x0 },
+ { 0x11168, 0x0 },
+ { 0x11268, 0x0 },
+ { 0x11368, 0x0 },
+ { 0x11468, 0x0 },
+ { 0x11568, 0x0 },
+ { 0x11668, 0x0 },
+ { 0x11768, 0x0 },
+ { 0x11868, 0x0 },
+ { 0x12068, 0x0 },
+ { 0x12168, 0x0 },
+ { 0x12268, 0x0 },
+ { 0x12368, 0x0 },
+ { 0x12468, 0x0 },
+ { 0x12568, 0x0 },
+ { 0x12668, 0x0 },
+ { 0x12768, 0x0 },
+ { 0x12868, 0x0 },
+ { 0x13068, 0x0 },
+ { 0x13168, 0x0 },
+ { 0x13268, 0x0 },
+ { 0x13368, 0x0 },
+ { 0x13468, 0x0 },
+ { 0x13568, 0x0 },
+ { 0x13668, 0x0 },
+ { 0x13768, 0x0 },
+ { 0x13868, 0x0 },
+ { 0x10069, 0x0 },
+ { 0x10169, 0x0 },
+ { 0x10269, 0x0 },
+ { 0x10369, 0x0 },
+ { 0x10469, 0x0 },
+ { 0x10569, 0x0 },
+ { 0x10669, 0x0 },
+ { 0x10769, 0x0 },
+ { 0x10869, 0x0 },
+ { 0x11069, 0x0 },
+ { 0x11169, 0x0 },
+ { 0x11269, 0x0 },
+ { 0x11369, 0x0 },
+ { 0x11469, 0x0 },
+ { 0x11569, 0x0 },
+ { 0x11669, 0x0 },
+ { 0x11769, 0x0 },
+ { 0x11869, 0x0 },
+ { 0x12069, 0x0 },
+ { 0x12169, 0x0 },
+ { 0x12269, 0x0 },
+ { 0x12369, 0x0 },
+ { 0x12469, 0x0 },
+ { 0x12569, 0x0 },
+ { 0x12669, 0x0 },
+ { 0x12769, 0x0 },
+ { 0x12869, 0x0 },
+ { 0x13069, 0x0 },
+ { 0x13169, 0x0 },
+ { 0x13269, 0x0 },
+ { 0x13369, 0x0 },
+ { 0x13469, 0x0 },
+ { 0x13569, 0x0 },
+ { 0x13669, 0x0 },
+ { 0x13769, 0x0 },
+ { 0x13869, 0x0 },
+ { 0x1008c, 0x0 },
+ { 0x11008c, 0x0 },
+ { 0x21008c, 0x0 },
+ { 0x1018c, 0x0 },
+ { 0x11018c, 0x0 },
+ { 0x21018c, 0x0 },
+ { 0x1108c, 0x0 },
+ { 0x11108c, 0x0 },
+ { 0x21108c, 0x0 },
+ { 0x1118c, 0x0 },
+ { 0x11118c, 0x0 },
+ { 0x21118c, 0x0 },
+ { 0x1208c, 0x0 },
+ { 0x11208c, 0x0 },
+ { 0x21208c, 0x0 },
+ { 0x1218c, 0x0 },
+ { 0x11218c, 0x0 },
+ { 0x21218c, 0x0 },
+ { 0x1308c, 0x0 },
+ { 0x11308c, 0x0 },
+ { 0x21308c, 0x0 },
+ { 0x1318c, 0x0 },
+ { 0x11318c, 0x0 },
+ { 0x21318c, 0x0 },
+ { 0x1008d, 0x0 },
+ { 0x11008d, 0x0 },
+ { 0x21008d, 0x0 },
+ { 0x1018d, 0x0 },
+ { 0x11018d, 0x0 },
+ { 0x21018d, 0x0 },
+ { 0x1108d, 0x0 },
+ { 0x11108d, 0x0 },
+ { 0x21108d, 0x0 },
+ { 0x1118d, 0x0 },
+ { 0x11118d, 0x0 },
+ { 0x21118d, 0x0 },
+ { 0x1208d, 0x0 },
+ { 0x11208d, 0x0 },
+ { 0x21208d, 0x0 },
+ { 0x1218d, 0x0 },
+ { 0x11218d, 0x0 },
+ { 0x21218d, 0x0 },
+ { 0x1308d, 0x0 },
+ { 0x11308d, 0x0 },
+ { 0x21308d, 0x0 },
+ { 0x1318d, 0x0 },
+ { 0x11318d, 0x0 },
+ { 0x21318d, 0x0 },
+ { 0x100c0, 0x0 },
+ { 0x1100c0, 0x0 },
+ { 0x2100c0, 0x0 },
+ { 0x101c0, 0x0 },
+ { 0x1101c0, 0x0 },
+ { 0x2101c0, 0x0 },
+ { 0x102c0, 0x0 },
+ { 0x1102c0, 0x0 },
+ { 0x2102c0, 0x0 },
+ { 0x103c0, 0x0 },
+ { 0x1103c0, 0x0 },
+ { 0x2103c0, 0x0 },
+ { 0x104c0, 0x0 },
+ { 0x1104c0, 0x0 },
+ { 0x2104c0, 0x0 },
+ { 0x105c0, 0x0 },
+ { 0x1105c0, 0x0 },
+ { 0x2105c0, 0x0 },
+ { 0x106c0, 0x0 },
+ { 0x1106c0, 0x0 },
+ { 0x2106c0, 0x0 },
+ { 0x107c0, 0x0 },
+ { 0x1107c0, 0x0 },
+ { 0x2107c0, 0x0 },
+ { 0x108c0, 0x0 },
+ { 0x1108c0, 0x0 },
+ { 0x2108c0, 0x0 },
+ { 0x110c0, 0x0 },
+ { 0x1110c0, 0x0 },
+ { 0x2110c0, 0x0 },
+ { 0x111c0, 0x0 },
+ { 0x1111c0, 0x0 },
+ { 0x2111c0, 0x0 },
+ { 0x112c0, 0x0 },
+ { 0x1112c0, 0x0 },
+ { 0x2112c0, 0x0 },
+ { 0x113c0, 0x0 },
+ { 0x1113c0, 0x0 },
+ { 0x2113c0, 0x0 },
+ { 0x114c0, 0x0 },
+ { 0x1114c0, 0x0 },
+ { 0x2114c0, 0x0 },
+ { 0x115c0, 0x0 },
+ { 0x1115c0, 0x0 },
+ { 0x2115c0, 0x0 },
+ { 0x116c0, 0x0 },
+ { 0x1116c0, 0x0 },
+ { 0x2116c0, 0x0 },
+ { 0x117c0, 0x0 },
+ { 0x1117c0, 0x0 },
+ { 0x2117c0, 0x0 },
+ { 0x118c0, 0x0 },
+ { 0x1118c0, 0x0 },
+ { 0x2118c0, 0x0 },
+ { 0x120c0, 0x0 },
+ { 0x1120c0, 0x0 },
+ { 0x2120c0, 0x0 },
+ { 0x121c0, 0x0 },
+ { 0x1121c0, 0x0 },
+ { 0x2121c0, 0x0 },
+ { 0x122c0, 0x0 },
+ { 0x1122c0, 0x0 },
+ { 0x2122c0, 0x0 },
+ { 0x123c0, 0x0 },
+ { 0x1123c0, 0x0 },
+ { 0x2123c0, 0x0 },
+ { 0x124c0, 0x0 },
+ { 0x1124c0, 0x0 },
+ { 0x2124c0, 0x0 },
+ { 0x125c0, 0x0 },
+ { 0x1125c0, 0x0 },
+ { 0x2125c0, 0x0 },
+ { 0x126c0, 0x0 },
+ { 0x1126c0, 0x0 },
+ { 0x2126c0, 0x0 },
+ { 0x127c0, 0x0 },
+ { 0x1127c0, 0x0 },
+ { 0x2127c0, 0x0 },
+ { 0x128c0, 0x0 },
+ { 0x1128c0, 0x0 },
+ { 0x2128c0, 0x0 },
+ { 0x130c0, 0x0 },
+ { 0x1130c0, 0x0 },
+ { 0x2130c0, 0x0 },
+ { 0x131c0, 0x0 },
+ { 0x1131c0, 0x0 },
+ { 0x2131c0, 0x0 },
+ { 0x132c0, 0x0 },
+ { 0x1132c0, 0x0 },
+ { 0x2132c0, 0x0 },
+ { 0x133c0, 0x0 },
+ { 0x1133c0, 0x0 },
+ { 0x2133c0, 0x0 },
+ { 0x134c0, 0x0 },
+ { 0x1134c0, 0x0 },
+ { 0x2134c0, 0x0 },
+ { 0x135c0, 0x0 },
+ { 0x1135c0, 0x0 },
+ { 0x2135c0, 0x0 },
+ { 0x136c0, 0x0 },
+ { 0x1136c0, 0x0 },
+ { 0x2136c0, 0x0 },
+ { 0x137c0, 0x0 },
+ { 0x1137c0, 0x0 },
+ { 0x2137c0, 0x0 },
+ { 0x138c0, 0x0 },
+ { 0x1138c0, 0x0 },
+ { 0x2138c0, 0x0 },
+ { 0x100c1, 0x0 },
+ { 0x1100c1, 0x0 },
+ { 0x2100c1, 0x0 },
+ { 0x101c1, 0x0 },
+ { 0x1101c1, 0x0 },
+ { 0x2101c1, 0x0 },
+ { 0x102c1, 0x0 },
+ { 0x1102c1, 0x0 },
+ { 0x2102c1, 0x0 },
+ { 0x103c1, 0x0 },
+ { 0x1103c1, 0x0 },
+ { 0x2103c1, 0x0 },
+ { 0x104c1, 0x0 },
+ { 0x1104c1, 0x0 },
+ { 0x2104c1, 0x0 },
+ { 0x105c1, 0x0 },
+ { 0x1105c1, 0x0 },
+ { 0x2105c1, 0x0 },
+ { 0x106c1, 0x0 },
+ { 0x1106c1, 0x0 },
+ { 0x2106c1, 0x0 },
+ { 0x107c1, 0x0 },
+ { 0x1107c1, 0x0 },
+ { 0x2107c1, 0x0 },
+ { 0x108c1, 0x0 },
+ { 0x1108c1, 0x0 },
+ { 0x2108c1, 0x0 },
+ { 0x110c1, 0x0 },
+ { 0x1110c1, 0x0 },
+ { 0x2110c1, 0x0 },
+ { 0x111c1, 0x0 },
+ { 0x1111c1, 0x0 },
+ { 0x2111c1, 0x0 },
+ { 0x112c1, 0x0 },
+ { 0x1112c1, 0x0 },
+ { 0x2112c1, 0x0 },
+ { 0x113c1, 0x0 },
+ { 0x1113c1, 0x0 },
+ { 0x2113c1, 0x0 },
+ { 0x114c1, 0x0 },
+ { 0x1114c1, 0x0 },
+ { 0x2114c1, 0x0 },
+ { 0x115c1, 0x0 },
+ { 0x1115c1, 0x0 },
+ { 0x2115c1, 0x0 },
+ { 0x116c1, 0x0 },
+ { 0x1116c1, 0x0 },
+ { 0x2116c1, 0x0 },
+ { 0x117c1, 0x0 },
+ { 0x1117c1, 0x0 },
+ { 0x2117c1, 0x0 },
+ { 0x118c1, 0x0 },
+ { 0x1118c1, 0x0 },
+ { 0x2118c1, 0x0 },
+ { 0x120c1, 0x0 },
+ { 0x1120c1, 0x0 },
+ { 0x2120c1, 0x0 },
+ { 0x121c1, 0x0 },
+ { 0x1121c1, 0x0 },
+ { 0x2121c1, 0x0 },
+ { 0x122c1, 0x0 },
+ { 0x1122c1, 0x0 },
+ { 0x2122c1, 0x0 },
+ { 0x123c1, 0x0 },
+ { 0x1123c1, 0x0 },
+ { 0x2123c1, 0x0 },
+ { 0x124c1, 0x0 },
+ { 0x1124c1, 0x0 },
+ { 0x2124c1, 0x0 },
+ { 0x125c1, 0x0 },
+ { 0x1125c1, 0x0 },
+ { 0x2125c1, 0x0 },
+ { 0x126c1, 0x0 },
+ { 0x1126c1, 0x0 },
+ { 0x2126c1, 0x0 },
+ { 0x127c1, 0x0 },
+ { 0x1127c1, 0x0 },
+ { 0x2127c1, 0x0 },
+ { 0x128c1, 0x0 },
+ { 0x1128c1, 0x0 },
+ { 0x2128c1, 0x0 },
+ { 0x130c1, 0x0 },
+ { 0x1130c1, 0x0 },
+ { 0x2130c1, 0x0 },
+ { 0x131c1, 0x0 },
+ { 0x1131c1, 0x0 },
+ { 0x2131c1, 0x0 },
+ { 0x132c1, 0x0 },
+ { 0x1132c1, 0x0 },
+ { 0x2132c1, 0x0 },
+ { 0x133c1, 0x0 },
+ { 0x1133c1, 0x0 },
+ { 0x2133c1, 0x0 },
+ { 0x134c1, 0x0 },
+ { 0x1134c1, 0x0 },
+ { 0x2134c1, 0x0 },
+ { 0x135c1, 0x0 },
+ { 0x1135c1, 0x0 },
+ { 0x2135c1, 0x0 },
+ { 0x136c1, 0x0 },
+ { 0x1136c1, 0x0 },
+ { 0x2136c1, 0x0 },
+ { 0x137c1, 0x0 },
+ { 0x1137c1, 0x0 },
+ { 0x2137c1, 0x0 },
+ { 0x138c1, 0x0 },
+ { 0x1138c1, 0x0 },
+ { 0x2138c1, 0x0 },
+ { 0x10020, 0x0 },
+ { 0x110020, 0x0 },
+ { 0x210020, 0x0 },
+ { 0x11020, 0x0 },
+ { 0x111020, 0x0 },
+ { 0x211020, 0x0 },
+ { 0x12020, 0x0 },
+ { 0x112020, 0x0 },
+ { 0x212020, 0x0 },
+ { 0x13020, 0x0 },
+ { 0x113020, 0x0 },
+ { 0x213020, 0x0 },
+ { 0x20072, 0x0 },
+ { 0x20073, 0x0 },
+ { 0x20074, 0x0 },
+ { 0x100aa, 0x0 },
+ { 0x110aa, 0x0 },
+ { 0x120aa, 0x0 },
+ { 0x130aa, 0x0 },
+ { 0x20010, 0x0 },
+ { 0x120010, 0x0 },
+ { 0x220010, 0x0 },
+ { 0x20011, 0x0 },
+ { 0x120011, 0x0 },
+ { 0x220011, 0x0 },
+ { 0x100ae, 0x0 },
+ { 0x1100ae, 0x0 },
+ { 0x2100ae, 0x0 },
+ { 0x100af, 0x0 },
+ { 0x1100af, 0x0 },
+ { 0x2100af, 0x0 },
+ { 0x110ae, 0x0 },
+ { 0x1110ae, 0x0 },
+ { 0x2110ae, 0x0 },
+ { 0x110af, 0x0 },
+ { 0x1110af, 0x0 },
+ { 0x2110af, 0x0 },
+ { 0x120ae, 0x0 },
+ { 0x1120ae, 0x0 },
+ { 0x2120ae, 0x0 },
+ { 0x120af, 0x0 },
+ { 0x1120af, 0x0 },
+ { 0x2120af, 0x0 },
+ { 0x130ae, 0x0 },
+ { 0x1130ae, 0x0 },
+ { 0x2130ae, 0x0 },
+ { 0x130af, 0x0 },
+ { 0x1130af, 0x0 },
+ { 0x2130af, 0x0 },
+ { 0x20020, 0x0 },
+ { 0x120020, 0x0 },
+ { 0x220020, 0x0 },
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x0 },
+ { 0x100a2, 0x0 },
+ { 0x100a3, 0x0 },
+ { 0x100a4, 0x0 },
+ { 0x100a5, 0x0 },
+ { 0x100a6, 0x0 },
+ { 0x100a7, 0x0 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x0 },
+ { 0x110a2, 0x0 },
+ { 0x110a3, 0x0 },
+ { 0x110a4, 0x0 },
+ { 0x110a5, 0x0 },
+ { 0x110a6, 0x0 },
+ { 0x110a7, 0x0 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x0 },
+ { 0x120a2, 0x0 },
+ { 0x120a3, 0x0 },
+ { 0x120a4, 0x0 },
+ { 0x120a5, 0x0 },
+ { 0x120a6, 0x0 },
+ { 0x120a7, 0x0 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x0 },
+ { 0x130a2, 0x0 },
+ { 0x130a3, 0x0 },
+ { 0x130a4, 0x0 },
+ { 0x130a5, 0x0 },
+ { 0x130a6, 0x0 },
+ { 0x130a7, 0x0 },
+ { 0x2007c, 0x0 },
+ { 0x12007c, 0x0 },
+ { 0x22007c, 0x0 },
+ { 0x2007d, 0x0 },
+ { 0x12007d, 0x0 },
+ { 0x22007d, 0x0 },
+ { 0x400fd, 0x0 },
+ { 0x400c0, 0x0 },
+ { 0x90201, 0x0 },
+ { 0x190201, 0x0 },
+ { 0x290201, 0x0 },
+ { 0x90202, 0x0 },
+ { 0x190202, 0x0 },
+ { 0x290202, 0x0 },
+ { 0x90203, 0x0 },
+ { 0x190203, 0x0 },
+ { 0x290203, 0x0 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x90205, 0x0 },
+ { 0x190205, 0x0 },
+ { 0x290205, 0x0 },
+ { 0x90206, 0x0 },
+ { 0x190206, 0x0 },
+ { 0x290206, 0x0 },
+ { 0x90207, 0x0 },
+ { 0x190207, 0x0 },
+ { 0x290207, 0x0 },
+ { 0x90208, 0x0 },
+ { 0x190208, 0x0 },
+ { 0x290208, 0x0 },
+ { 0x10062, 0x0 },
+ { 0x10162, 0x0 },
+ { 0x10262, 0x0 },
+ { 0x10362, 0x0 },
+ { 0x10462, 0x0 },
+ { 0x10562, 0x0 },
+ { 0x10662, 0x0 },
+ { 0x10762, 0x0 },
+ { 0x10862, 0x0 },
+ { 0x11062, 0x0 },
+ { 0x11162, 0x0 },
+ { 0x11262, 0x0 },
+ { 0x11362, 0x0 },
+ { 0x11462, 0x0 },
+ { 0x11562, 0x0 },
+ { 0x11662, 0x0 },
+ { 0x11762, 0x0 },
+ { 0x11862, 0x0 },
+ { 0x12062, 0x0 },
+ { 0x12162, 0x0 },
+ { 0x12262, 0x0 },
+ { 0x12362, 0x0 },
+ { 0x12462, 0x0 },
+ { 0x12562, 0x0 },
+ { 0x12662, 0x0 },
+ { 0x12762, 0x0 },
+ { 0x12862, 0x0 },
+ { 0x13062, 0x0 },
+ { 0x13162, 0x0 },
+ { 0x13262, 0x0 },
+ { 0x13362, 0x0 },
+ { 0x13462, 0x0 },
+ { 0x13562, 0x0 },
+ { 0x13662, 0x0 },
+ { 0x13762, 0x0 },
+ { 0x13862, 0x0 },
+ { 0x20077, 0x0 },
+ { 0x10001, 0x0 },
+ { 0x11001, 0x0 },
+ { 0x12001, 0x0 },
+ { 0x13001, 0x0 },
+ { 0x10040, 0x0 },
+ { 0x10140, 0x0 },
+ { 0x10240, 0x0 },
+ { 0x10340, 0x0 },
+ { 0x10440, 0x0 },
+ { 0x10540, 0x0 },
+ { 0x10640, 0x0 },
+ { 0x10740, 0x0 },
+ { 0x10840, 0x0 },
+ { 0x10030, 0x0 },
+ { 0x10130, 0x0 },
+ { 0x10230, 0x0 },
+ { 0x10330, 0x0 },
+ { 0x10430, 0x0 },
+ { 0x10530, 0x0 },
+ { 0x10630, 0x0 },
+ { 0x10730, 0x0 },
+ { 0x10830, 0x0 },
+ { 0x11040, 0x0 },
+ { 0x11140, 0x0 },
+ { 0x11240, 0x0 },
+ { 0x11340, 0x0 },
+ { 0x11440, 0x0 },
+ { 0x11540, 0x0 },
+ { 0x11640, 0x0 },
+ { 0x11740, 0x0 },
+ { 0x11840, 0x0 },
+ { 0x11030, 0x0 },
+ { 0x11130, 0x0 },
+ { 0x11230, 0x0 },
+ { 0x11330, 0x0 },
+ { 0x11430, 0x0 },
+ { 0x11530, 0x0 },
+ { 0x11630, 0x0 },
+ { 0x11730, 0x0 },
+ { 0x11830, 0x0 },
+ { 0x12040, 0x0 },
+ { 0x12140, 0x0 },
+ { 0x12240, 0x0 },
+ { 0x12340, 0x0 },
+ { 0x12440, 0x0 },
+ { 0x12540, 0x0 },
+ { 0x12640, 0x0 },
+ { 0x12740, 0x0 },
+ { 0x12840, 0x0 },
+ { 0x12030, 0x0 },
+ { 0x12130, 0x0 },
+ { 0x12230, 0x0 },
+ { 0x12330, 0x0 },
+ { 0x12430, 0x0 },
+ { 0x12530, 0x0 },
+ { 0x12630, 0x0 },
+ { 0x12730, 0x0 },
+ { 0x12830, 0x0 },
+ { 0x13040, 0x0 },
+ { 0x13140, 0x0 },
+ { 0x13240, 0x0 },
+ { 0x13340, 0x0 },
+ { 0x13440, 0x0 },
+ { 0x13540, 0x0 },
+ { 0x13640, 0x0 },
+ { 0x13740, 0x0 },
+ { 0x13840, 0x0 },
+ { 0x13030, 0x0 },
+ { 0x13130, 0x0 },
+ { 0x13230, 0x0 },
+ { 0x13330, 0x0 },
+ { 0x13430, 0x0 },
+ { 0x13530, 0x0 },
+ { 0x13630, 0x0 },
+ { 0x13730, 0x0 },
+ { 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54000, 0x0 },
+ { 0x54001, 0x0 },
+ { 0x54002, 0x0 },
+ { 0x54003, 0xbb8 },
+ { 0x54004, 0x2 },
+ { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
+ { 0x54006, LPDDR4_PHY_VREF_VALUE },
+ { 0x54007, 0x0 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400a, 0x0 },
+ { 0x5400b, 0x2 },
+ { 0x5400c, 0x0 },
+ { 0x5400d, 0x0 },
+ { 0x5400e, 0x0 },
+ { 0x5400f, 0x0 },
+ { 0x54010, 0x0 },
+ { 0x54011, 0x0 },
+ { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
+ { 0x54013, 0x0 },
+ { 0x54014, 0x0 },
+ { 0x54015, 0x0 },
+ { 0x54016, 0x0 },
+ { 0x54017, 0x0 },
+ { 0x54018, 0x0 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d08 },
+ { 0x5401d, 0x0 },
+ { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d08 },
+ { 0x54023, 0x0 },
+ { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
+ { 0x54025, 0x0 },
+ { 0x54026, 0x0 },
+ { 0x54027, 0x0 },
+ { 0x54028, 0x0 },
+ { 0x54029, 0x0 },
+ { 0x5402a, 0x0 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, LPDDR4_CS },
+ { 0x5402d, 0x0 },
+ { 0x5402e, 0x0 },
+ { 0x5402f, 0x0 },
+ { 0x54030, 0x0 },
+ { 0x54031, 0x0 },
+ { 0x54032, 0xd400 },
+ { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x84d },
+ { 0x54036, 0x4d },
+ { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+ { 0x54038, 0xd400 },
+ { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x84d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
+ { 0x5403e, 0x0 },
+ { 0x5403f, 0x0 },
+ { 0x54040, 0x0 },
+ { 0x54041, 0x0 },
+ { 0x54042, 0x0 },
+ { 0x54043, 0x0 },
+ { 0x54044, 0x0 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp1_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54000, 0x0 },
+ { 0x54001, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },/* PHY Ron/Rtt */
+ { 0x54006, LPDDR4_PHY_VREF_VALUE },
+ { 0x54007, 0x0 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400a, 0x0 },
+ { 0x5400b, 0x2 },
+ { 0x5400c, 0x0 },
+ { 0x5400d, 0x0 },
+ { 0x5400e, 0x0 },
+ { 0x5400f, 0x0 },
+ { 0x54010, 0x0 },
+ { 0x54011, 0x0 },
+ { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
+ { 0x54013, 0x0 },
+ { 0x54014, 0x0 },
+ { 0x54015, 0x0 },
+ { 0x54016, 0x0 },
+ { 0x54017, 0x0 },
+ { 0x54018, 0x0 },
+ { 0x54019, 0x84 },
+ { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d08 },
+ { 0x5401d, 0x0 },
+ { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+ { 0x5401f, 0x84 },
+ { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d08 },
+ { 0x54023, 0x0 },
+ { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
+ { 0x54025, 0x0 },
+ { 0x54026, 0x0 },
+ { 0x54027, 0x0 },
+ { 0x54028, 0x0 },
+ { 0x54029, 0x0 },
+ { 0x5402a, 0x0 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, LPDDR4_CS },
+ { 0x5402d, 0x0 },
+ { 0x5402e, 0x0 },
+ { 0x5402f, 0x0 },
+ { 0x54030, 0x0 },
+ { 0x54031, 0x0 },
+ { 0x54032, 0x8400 },
+ { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x84d },
+ { 0x54036, 0x4d },
+ { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+ { 0x54038, 0x8400 },
+ { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x84d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
+ { 0x5403e, 0x0 },
+ { 0x5403f, 0x0 },
+ { 0x54040, 0x0 },
+ { 0x54041, 0x0 },
+ { 0x54042, 0x0 },
+ { 0x54043, 0x0 },
+ { 0x54044, 0x0 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp2_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54000, 0x0 },
+ { 0x54001, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
+ { 0x54006, LPDDR4_PHY_VREF_VALUE },
+ { 0x54007, 0x0 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400a, 0x0 },
+ { 0x5400b, 0x2 },
+ { 0x5400c, 0x0 },
+ { 0x5400d, 0x0 },
+ { 0x5400e, 0x0 },
+ { 0x5400f, 0x0 },
+ { 0x54010, 0x0 },
+ { 0x54011, 0x0 },
+ { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
+ { 0x54013, 0x0 },
+ { 0x54014, 0x0 },
+ { 0x54015, 0x0 },
+ { 0x54016, 0x0 },
+ { 0x54017, 0x0 },
+ { 0x54018, 0x0 },
+ { 0x54019, 0x84 },
+ { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d08 },
+ { 0x5401d, 0x0 },
+ { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+ { 0x5401f, 0x84 },
+ { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d08 },
+ { 0x54023, 0x0 },
+ { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
+ { 0x54025, 0x0 },
+ { 0x54026, 0x0 },
+ { 0x54027, 0x0 },
+ { 0x54028, 0x0 },
+ { 0x54029, 0x0 },
+ { 0x5402a, 0x0 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, LPDDR4_CS },
+ { 0x5402d, 0x0 },
+ { 0x5402e, 0x0 },
+ { 0x5402f, 0x0 },
+ { 0x54030, 0x0 },
+ { 0x54031, 0x0 },
+ { 0x54032, 0x8400 },
+ { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x84d },
+ { 0x54036, 0x4d },
+ { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+ { 0x54038, 0x8400 },
+ { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x84d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
+ { 0x5403e, 0x0 },
+ { 0x5403f, 0x0 },
+ { 0x54040, 0x0 },
+ { 0x54041, 0x0 },
+ { 0x54042, 0x0 },
+ { 0x54043, 0x0 },
+ { 0x54044, 0x0 },
+ { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54000, 0x0 },
+ { 0x54001, 0x0 },
+ { 0x54002, 0x0 },
+ { 0x54003, 0xbb8 },
+ { 0x54004, 0x2 },
+ { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
+ { 0x54006, LPDDR4_PHY_VREF_VALUE },
+ { 0x54007, 0x0 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400a, 0x0 },
+ { 0x5400b, 0x2 },
+ { 0x5400c, 0x0 },
+ { 0x5400d, 0x0 },
+ { 0x5400e, 0x0 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54011, 0x0 },
+ { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
+ { 0x54013, 0x0 },
+ { 0x54014, 0x0 },
+ { 0x54015, 0x0 },
+ { 0x54016, 0x0 },
+ { 0x54017, 0x0 },
+ { 0x54018, 0x0 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d08 },
+ { 0x5401d, 0x0 },
+ { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d08 },
+ { 0x54023, 0x0 },
+ { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
+ { 0x54025, 0x0 },
+ { 0x54026, 0x0 },
+ { 0x54027, 0x0 },
+ { 0x54028, 0x0 },
+ { 0x54029, 0x0 },
+ { 0x5402a, 0x0 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, LPDDR4_CS },
+ { 0x5402d, 0x0 },
+ { 0x5402e, 0x0 },
+ { 0x5402f, 0x0 },
+ { 0x54030, 0x0 },
+ { 0x54031, 0x0 },
+ { 0x54032, 0xd400 },
+ { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x84d },
+ { 0x54036, 0x4d },
+ { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+ { 0x54038, 0xd400 },
+ { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x84d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
+ { 0x5403e, 0x0 },
+ { 0x5403f, 0x0 },
+ { 0x54040, 0x0 },
+ { 0x54041, 0x0 },
+ { 0x54042, 0x0 },
+ { 0x54043, 0x0 },
+ { 0x54044, 0x0 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param lpddr4_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x0 },
+ { 0x90033, 0xe8 },
+ { 0x90034, 0x109 },
+ { 0x90035, 0x2 },
+ { 0x90036, 0x10 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0xf },
+ { 0x90039, 0x7c0 },
+ { 0x9003a, 0x139 },
+ { 0x9003b, 0x44 },
+ { 0x9003c, 0x630 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x14f },
+ { 0x9003f, 0x630 },
+ { 0x90040, 0x159 },
+ { 0x90041, 0x47 },
+ { 0x90042, 0x630 },
+ { 0x90043, 0x149 },
+ { 0x90044, 0x4f },
+ { 0x90045, 0x630 },
+ { 0x90046, 0x179 },
+ { 0x90047, 0x8 },
+ { 0x90048, 0xe0 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x7c8 },
+ { 0x9004c, 0x109 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x1 },
+ { 0x9004f, 0x8 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x45a },
+ { 0x90052, 0x9 },
+ { 0x90053, 0x0 },
+ { 0x90054, 0x448 },
+ { 0x90055, 0x109 },
+ { 0x90056, 0x40 },
+ { 0x90057, 0x630 },
+ { 0x90058, 0x179 },
+ { 0x90059, 0x1 },
+ { 0x9005a, 0x618 },
+ { 0x9005b, 0x109 },
+ { 0x9005c, 0x40c0 },
+ { 0x9005d, 0x630 },
+ { 0x9005e, 0x149 },
+ { 0x9005f, 0x8 },
+ { 0x90060, 0x4 },
+ { 0x90061, 0x48 },
+ { 0x90062, 0x4040 },
+ { 0x90063, 0x630 },
+ { 0x90064, 0x149 },
+ { 0x90065, 0x0 },
+ { 0x90066, 0x4 },
+ { 0x90067, 0x48 },
+ { 0x90068, 0x40 },
+ { 0x90069, 0x630 },
+ { 0x9006a, 0x149 },
+ { 0x9006b, 0x10 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x18 },
+ { 0x9006e, 0x0 },
+ { 0x9006f, 0x4 },
+ { 0x90070, 0x78 },
+ { 0x90071, 0x549 },
+ { 0x90072, 0x630 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0xd49 },
+ { 0x90075, 0x630 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x94a },
+ { 0x90078, 0x630 },
+ { 0x90079, 0x159 },
+ { 0x9007a, 0x441 },
+ { 0x9007b, 0x630 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x42 },
+ { 0x9007e, 0x630 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x1 },
+ { 0x90081, 0x630 },
+ { 0x90082, 0x149 },
+ { 0x90083, 0x0 },
+ { 0x90084, 0xe0 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0xa },
+ { 0x90087, 0x10 },
+ { 0x90088, 0x109 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x149 },
+ { 0x9008c, 0x9 },
+ { 0x9008d, 0x3c0 },
+ { 0x9008e, 0x159 },
+ { 0x9008f, 0x18 },
+ { 0x90090, 0x10 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x0 },
+ { 0x90093, 0x3c0 },
+ { 0x90094, 0x109 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x48 },
+ { 0x90098, 0x18 },
+ { 0x90099, 0x4 },
+ { 0x9009a, 0x58 },
+ { 0x9009b, 0xa },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x2 },
+ { 0x9009f, 0x10 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x5 },
+ { 0x900a2, 0x7c0 },
+ { 0x900a3, 0x109 },
+ { 0x900a4, 0x10 },
+ { 0x900a5, 0x10 },
+ { 0x900a6, 0x109 },
+ { 0x40000, 0x811 },
+ { 0x40020, 0x880 },
+ { 0x40040, 0x0 },
+ { 0x40060, 0x0 },
+ { 0x40001, 0x4008 },
+ { 0x40021, 0x83 },
+ { 0x40041, 0x4f },
+ { 0x40061, 0x0 },
+ { 0x40002, 0x4040 },
+ { 0x40022, 0x83 },
+ { 0x40042, 0x51 },
+ { 0x40062, 0x0 },
+ { 0x40003, 0x811 },
+ { 0x40023, 0x880 },
+ { 0x40043, 0x0 },
+ { 0x40063, 0x0 },
+ { 0x40004, 0x720 },
+ { 0x40024, 0xf },
+ { 0x40044, 0x1740 },
+ { 0x40064, 0x0 },
+ { 0x40005, 0x16 },
+ { 0x40025, 0x83 },
+ { 0x40045, 0x4b },
+ { 0x40065, 0x0 },
+ { 0x40006, 0x716 },
+ { 0x40026, 0xf },
+ { 0x40046, 0x2001 },
+ { 0x40066, 0x0 },
+ { 0x40007, 0x716 },
+ { 0x40027, 0xf },
+ { 0x40047, 0x2800 },
+ { 0x40067, 0x0 },
+ { 0x40008, 0x716 },
+ { 0x40028, 0xf },
+ { 0x40048, 0xf00 },
+ { 0x40068, 0x0 },
+ { 0x40009, 0x720 },
+ { 0x40029, 0xf },
+ { 0x40049, 0x1400 },
+ { 0x40069, 0x0 },
+ { 0x4000a, 0xe08 },
+ { 0x4002a, 0xc15 },
+ { 0x4004a, 0x0 },
+ { 0x4006a, 0x0 },
+ { 0x4000b, 0x623 },
+ { 0x4002b, 0x15 },
+ { 0x4004b, 0x0 },
+ { 0x4006b, 0x0 },
+ { 0x4000c, 0x4028 },
+ { 0x4002c, 0x80 },
+ { 0x4004c, 0x0 },
+ { 0x4006c, 0x0 },
+ { 0x4000d, 0xe08 },
+ { 0x4002d, 0xc1a },
+ { 0x4004d, 0x0 },
+ { 0x4006d, 0x0 },
+ { 0x4000e, 0x623 },
+ { 0x4002e, 0x1a },
+ { 0x4004e, 0x0 },
+ { 0x4006e, 0x0 },
+ { 0x4000f, 0x4040 },
+ { 0x4002f, 0x80 },
+ { 0x4004f, 0x0 },
+ { 0x4006f, 0x0 },
+ { 0x40010, 0x2604 },
+ { 0x40030, 0x15 },
+ { 0x40050, 0x0 },
+ { 0x40070, 0x0 },
+ { 0x40011, 0x708 },
+ { 0x40031, 0x5 },
+ { 0x40051, 0x0 },
+ { 0x40071, 0x2002 },
+ { 0x40012, 0x8 },
+ { 0x40032, 0x80 },
+ { 0x40052, 0x0 },
+ { 0x40072, 0x0 },
+ { 0x40013, 0x2604 },
+ { 0x40033, 0x1a },
+ { 0x40053, 0x0 },
+ { 0x40073, 0x0 },
+ { 0x40014, 0x708 },
+ { 0x40034, 0xa },
+ { 0x40054, 0x0 },
+ { 0x40074, 0x2002 },
+ { 0x40015, 0x4040 },
+ { 0x40035, 0x80 },
+ { 0x40055, 0x0 },
+ { 0x40075, 0x0 },
+ { 0x40016, 0x60a },
+ { 0x40036, 0x15 },
+ { 0x40056, 0x1200 },
+ { 0x40076, 0x0 },
+ { 0x40017, 0x61a },
+ { 0x40037, 0x15 },
+ { 0x40057, 0x1300 },
+ { 0x40077, 0x0 },
+ { 0x40018, 0x60a },
+ { 0x40038, 0x1a },
+ { 0x40058, 0x1200 },
+ { 0x40078, 0x0 },
+ { 0x40019, 0x642 },
+ { 0x40039, 0x1a },
+ { 0x40059, 0x1300 },
+ { 0x40079, 0x0 },
+ { 0x4001a, 0x4808 },
+ { 0x4003a, 0x880 },
+ { 0x4005a, 0x0 },
+ { 0x4007a, 0x0 },
+ { 0x900a7, 0x0 },
+ { 0x900a8, 0x790 },
+ { 0x900a9, 0x11a },
+ { 0x900aa, 0x8 },
+ { 0x900ab, 0x7aa },
+ { 0x900ac, 0x2a },
+ { 0x900ad, 0x10 },
+ { 0x900ae, 0x7b2 },
+ { 0x900af, 0x2a },
+ { 0x900b0, 0x0 },
+ { 0x900b1, 0x7c8 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x10 },
+ { 0x900b4, 0x2a8 },
+ { 0x900b5, 0x129 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0x370 },
+ { 0x900b8, 0x129 },
+ { 0x900b9, 0xa },
+ { 0x900ba, 0x3c8 },
+ { 0x900bb, 0x1a9 },
+ { 0x900bc, 0xc },
+ { 0x900bd, 0x408 },
+ { 0x900be, 0x199 },
+ { 0x900bf, 0x14 },
+ { 0x900c0, 0x790 },
+ { 0x900c1, 0x11a },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x18 },
+ { 0x900c5, 0xe },
+ { 0x900c6, 0x408 },
+ { 0x900c7, 0x199 },
+ { 0x900c8, 0x8 },
+ { 0x900c9, 0x8568 },
+ { 0x900ca, 0x108 },
+ { 0x900cb, 0x18 },
+ { 0x900cc, 0x790 },
+ { 0x900cd, 0x16a },
+ { 0x900ce, 0x8 },
+ { 0x900cf, 0x1d8 },
+ { 0x900d0, 0x169 },
+ { 0x900d1, 0x10 },
+ { 0x900d2, 0x8558 },
+ { 0x900d3, 0x168 },
+ { 0x900d4, 0x70 },
+ { 0x900d5, 0x788 },
+ { 0x900d6, 0x16a },
+ { 0x900d7, 0x1ff8 },
+ { 0x900d8, 0x85a8 },
+ { 0x900d9, 0x1e8 },
+ { 0x900da, 0x50 },
+ { 0x900db, 0x798 },
+ { 0x900dc, 0x16a },
+ { 0x900dd, 0x60 },
+ { 0x900de, 0x7a0 },
+ { 0x900df, 0x16a },
+ { 0x900e0, 0x8 },
+ { 0x900e1, 0x8310 },
+ { 0x900e2, 0x168 },
+ { 0x900e3, 0x8 },
+ { 0x900e4, 0xa310 },
+ { 0x900e5, 0x168 },
+ { 0x900e6, 0xa },
+ { 0x900e7, 0x408 },
+ { 0x900e8, 0x169 },
+ { 0x900e9, 0x6e },
+ { 0x900ea, 0x0 },
+ { 0x900eb, 0x68 },
+ { 0x900ec, 0x0 },
+ { 0x900ed, 0x408 },
+ { 0x900ee, 0x169 },
+ { 0x900ef, 0x0 },
+ { 0x900f0, 0x8310 },
+ { 0x900f1, 0x168 },
+ { 0x900f2, 0x0 },
+ { 0x900f3, 0xa310 },
+ { 0x900f4, 0x168 },
+ { 0x900f5, 0x1ff8 },
+ { 0x900f6, 0x85a8 },
+ { 0x900f7, 0x1e8 },
+ { 0x900f8, 0x68 },
+ { 0x900f9, 0x798 },
+ { 0x900fa, 0x16a },
+ { 0x900fb, 0x78 },
+ { 0x900fc, 0x7a0 },
+ { 0x900fd, 0x16a },
+ { 0x900fe, 0x68 },
+ { 0x900ff, 0x790 },
+ { 0x90100, 0x16a },
+ { 0x90101, 0x8 },
+ { 0x90102, 0x8b10 },
+ { 0x90103, 0x168 },
+ { 0x90104, 0x8 },
+ { 0x90105, 0xab10 },
+ { 0x90106, 0x168 },
+ { 0x90107, 0xa },
+ { 0x90108, 0x408 },
+ { 0x90109, 0x169 },
+ { 0x9010a, 0x58 },
+ { 0x9010b, 0x0 },
+ { 0x9010c, 0x68 },
+ { 0x9010d, 0x0 },
+ { 0x9010e, 0x408 },
+ { 0x9010f, 0x169 },
+ { 0x90110, 0x0 },
+ { 0x90111, 0x8b10 },
+ { 0x90112, 0x168 },
+ { 0x90113, 0x0 },
+ { 0x90114, 0xab10 },
+ { 0x90115, 0x168 },
+ { 0x90116, 0x0 },
+ { 0x90117, 0x1d8 },
+ { 0x90118, 0x169 },
+ { 0x90119, 0x80 },
+ { 0x9011a, 0x790 },
+ { 0x9011b, 0x16a },
+ { 0x9011c, 0x18 },
+ { 0x9011d, 0x7aa },
+ { 0x9011e, 0x6a },
+ { 0x9011f, 0xa },
+ { 0x90120, 0x0 },
+ { 0x90121, 0x1e9 },
+ { 0x90122, 0x8 },
+ { 0x90123, 0x8080 },
+ { 0x90124, 0x108 },
+ { 0x90125, 0xf },
+ { 0x90126, 0x408 },
+ { 0x90127, 0x169 },
+ { 0x90128, 0xc },
+ { 0x90129, 0x0 },
+ { 0x9012a, 0x68 },
+ { 0x9012b, 0x9 },
+ { 0x9012c, 0x0 },
+ { 0x9012d, 0x1a9 },
+ { 0x9012e, 0x0 },
+ { 0x9012f, 0x408 },
+ { 0x90130, 0x169 },
+ { 0x90131, 0x0 },
+ { 0x90132, 0x8080 },
+ { 0x90133, 0x108 },
+ { 0x90134, 0x8 },
+ { 0x90135, 0x7aa },
+ { 0x90136, 0x6a },
+ { 0x90137, 0x0 },
+ { 0x90138, 0x8568 },
+ { 0x90139, 0x108 },
+ { 0x9013a, 0xb7 },
+ { 0x9013b, 0x790 },
+ { 0x9013c, 0x16a },
+ { 0x9013d, 0x1f },
+ { 0x9013e, 0x0 },
+ { 0x9013f, 0x68 },
+ { 0x90140, 0x8 },
+ { 0x90141, 0x8558 },
+ { 0x90142, 0x168 },
+ { 0x90143, 0xf },
+ { 0x90144, 0x408 },
+ { 0x90145, 0x169 },
+ { 0x90146, 0xc },
+ { 0x90147, 0x0 },
+ { 0x90148, 0x68 },
+ { 0x90149, 0x0 },
+ { 0x9014a, 0x408 },
+ { 0x9014b, 0x169 },
+ { 0x9014c, 0x0 },
+ { 0x9014d, 0x8558 },
+ { 0x9014e, 0x168 },
+ { 0x9014f, 0x8 },
+ { 0x90150, 0x3c8 },
+ { 0x90151, 0x1a9 },
+ { 0x90152, 0x3 },
+ { 0x90153, 0x370 },
+ { 0x90154, 0x129 },
+ { 0x90155, 0x20 },
+ { 0x90156, 0x2aa },
+ { 0x90157, 0x9 },
+ { 0x90158, 0x0 },
+ { 0x90159, 0x400 },
+ { 0x9015a, 0x10e },
+ { 0x9015b, 0x8 },
+ { 0x9015c, 0xe8 },
+ { 0x9015d, 0x109 },
+ { 0x9015e, 0x0 },
+ { 0x9015f, 0x8140 },
+ { 0x90160, 0x10c },
+ { 0x90161, 0x10 },
+ { 0x90162, 0x8138 },
+ { 0x90163, 0x10c },
+ { 0x90164, 0x8 },
+ { 0x90165, 0x7c8 },
+ { 0x90166, 0x101 },
+ { 0x90167, 0x8 },
+ { 0x90168, 0x0 },
+ { 0x90169, 0x8 },
+ { 0x9016a, 0x8 },
+ { 0x9016b, 0x448 },
+ { 0x9016c, 0x109 },
+ { 0x9016d, 0xf },
+ { 0x9016e, 0x7c0 },
+ { 0x9016f, 0x109 },
+ { 0x90170, 0x0 },
+ { 0x90171, 0xe8 },
+ { 0x90172, 0x109 },
+ { 0x90173, 0x47 },
+ { 0x90174, 0x630 },
+ { 0x90175, 0x109 },
+ { 0x90176, 0x8 },
+ { 0x90177, 0x618 },
+ { 0x90178, 0x109 },
+ { 0x90179, 0x8 },
+ { 0x9017a, 0xe0 },
+ { 0x9017b, 0x109 },
+ { 0x9017c, 0x0 },
+ { 0x9017d, 0x7c8 },
+ { 0x9017e, 0x109 },
+ { 0x9017f, 0x8 },
+ { 0x90180, 0x8140 },
+ { 0x90181, 0x10c },
+ { 0x90182, 0x0 },
+ { 0x90183, 0x1 },
+ { 0x90184, 0x8 },
+ { 0x90185, 0x8 },
+ { 0x90186, 0x4 },
+ { 0x90187, 0x8 },
+ { 0x90188, 0x8 },
+ { 0x90189, 0x7c8 },
+ { 0x9018a, 0x101 },
+ { 0x90006, 0x0 },
+ { 0x90007, 0x0 },
+ { 0x90008, 0x8 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x0 },
+ { 0x9000b, 0x0 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x9001f, 0x2a },
+ { 0x90026, 0x6a },
+ { 0x400d0, 0x0 },
+ { 0x400d1, 0x101 },
+ { 0x400d2, 0x105 },
+ { 0x400d3, 0x107 },
+ { 0x400d4, 0x10f },
+ { 0x400d5, 0x202 },
+ { 0x400d6, 0x20a },
+ { 0x400d7, 0x20b },
+ { 0x2003a, 0x2 },
+ { 0x2000b, 0x5d },
+ { 0x2000c, 0xbb },
+ { 0x2000d, 0x753 },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0xc },
+ { 0x12000c, 0x19 },
+ { 0x12000d, 0xfa },
+ { 0x12000e, 0x10 },
+ { 0x22000b, 0x3 },
+ { 0x22000c, 0x6 },
+ { 0x22000d, 0x3e },
+ { 0x22000e, 0x10 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0x60 },
+ { 0x90013, 0x6152 },
+ { 0x20010, 0x5a },
+ { 0x20011, 0x3 },
+ { 0x40080, 0xe0 },
+ { 0x40081, 0x12 },
+ { 0x40082, 0xe0 },
+ { 0x40083, 0x12 },
+ { 0x40084, 0xe0 },
+ { 0x40085, 0x12 },
+ { 0x140080, 0xe0 },
+ { 0x140081, 0x12 },
+ { 0x140082, 0xe0 },
+ { 0x140083, 0x12 },
+ { 0x140084, 0xe0 },
+ { 0x140085, 0x12 },
+ { 0x240080, 0xe0 },
+ { 0x240081, 0x12 },
+ { 0x240082, 0xe0 },
+ { 0x240083, 0x12 },
+ { 0x240084, 0xe0 },
+ { 0x240085, 0x12 },
+ { 0x400fd, 0xf },
+ { 0x10011, 0x1 },
+ { 0x10012, 0x1 },
+ { 0x10013, 0x180 },
+ { 0x10018, 0x1 },
+ { 0x10002, 0x6209 },
+ { 0x100b2, 0x1 },
+ { 0x101b4, 0x1 },
+ { 0x102b4, 0x1 },
+ { 0x103b4, 0x1 },
+ { 0x104b4, 0x1 },
+ { 0x105b4, 0x1 },
+ { 0x106b4, 0x1 },
+ { 0x107b4, 0x1 },
+ { 0x108b4, 0x1 },
+ { 0x11011, 0x1 },
+ { 0x11012, 0x1 },
+ { 0x11013, 0x180 },
+ { 0x11018, 0x1 },
+ { 0x11002, 0x6209 },
+ { 0x110b2, 0x1 },
+ { 0x111b4, 0x1 },
+ { 0x112b4, 0x1 },
+ { 0x113b4, 0x1 },
+ { 0x114b4, 0x1 },
+ { 0x115b4, 0x1 },
+ { 0x116b4, 0x1 },
+ { 0x117b4, 0x1 },
+ { 0x118b4, 0x1 },
+ { 0x12011, 0x1 },
+ { 0x12012, 0x1 },
+ { 0x12013, 0x180 },
+ { 0x12018, 0x1 },
+ { 0x12002, 0x6209 },
+ { 0x120b2, 0x1 },
+ { 0x121b4, 0x1 },
+ { 0x122b4, 0x1 },
+ { 0x123b4, 0x1 },
+ { 0x124b4, 0x1 },
+ { 0x125b4, 0x1 },
+ { 0x126b4, 0x1 },
+ { 0x127b4, 0x1 },
+ { 0x128b4, 0x1 },
+ { 0x13011, 0x1 },
+ { 0x13012, 0x1 },
+ { 0x13013, 0x180 },
+ { 0x13018, 0x1 },
+ { 0x13002, 0x6209 },
+ { 0x130b2, 0x1 },
+ { 0x131b4, 0x1 },
+ { 0x132b4, 0x1 },
+ { 0x133b4, 0x1 },
+ { 0x134b4, 0x1 },
+ { 0x135b4, 0x1 },
+ { 0x136b4, 0x1 },
+ { 0x137b4, 0x1 },
+ { 0x138b4, 0x1 },
+ { 0x2003a, 0x2 },
+ { 0xc0080, 0x2 },
+ { 0xd0000, 0x1 },
+};
+
+static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
+ {
+ /* P0 3000mts 1D */
+ .drate = 3000,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = lpddr4_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
+ }, {
+ /* P0 3000mts 2D */
+ .drate = 3000,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = lpddr4_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
+ }, {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = lpddr4_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
+ }, {
+ /* P1 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = lpddr4_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
+ },
+};
+
+/* lpddr4 timing config params on EVK board */
+struct dram_timing_info imx8mm_evk_dram_timing = {
+ .ddrc_cfg = lpddr4_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
+ .ddrphy_cfg = lpddr4_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
+ .fsp_msg = lpddr4_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
+ .ddrphy_trained_csr = lpddr4_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(lpddr4_ddrphy_trained_csr),
+ .ddrphy_pie = lpddr4_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
+};
diff --git a/arch/arm/boards/nxp-imx8mq-evk/ddr.h b/arch/arm/boards/nxp-imx8mq-evk/ddr.h
index 65115db..fd09ad6 100644
--- a/arch/arm/boards/nxp-imx8mq-evk/ddr.h
+++ b/arch/arm/boards/nxp-imx8mq-evk/ddr.h
@@ -8,7 +8,7 @@
*/
#include <common.h>
#include <io.h>
-#include <mach/imx8-ddrc.h>
+#include <soc/imx8m/ddr.h>
/*
* Code generated by i.MX8 M DDR Tool doesn't have any prefixes in the
@@ -20,10 +20,3 @@
void nxp_imx8mq_evk_ddr_init(void);
void nxp_imx8mq_evk_ddr_cfg_phy(void);
-
-#define FW_1D_IMAGE lpddr4_pmu_train_1d_imem_bin, \
- lpddr4_pmu_train_1d_dmem_bin
-#define FW_2D_IMAGE lpddr4_pmu_train_2d_imem_bin, \
- lpddr4_pmu_train_2d_dmem_bin
-
-
diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
index 101ce60..39358af 100644
--- a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
+++ b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
@@ -1,13 +1,14 @@
// SPDX-License-Identifier: GPL-2.0
#include <common.h>
+#include <firmware.h>
#include <linux/sizes.h>
#include <mach/generic.h>
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
-#include <mach/imx8-ccm-regs.h>
-#include <mach/iomux-mx8.h>
-#include <mach/imx8-ddrc.h>
+#include <mach/imx8m-ccm-regs.h>
+#include <mach/iomux-mx8mq.h>
+#include <soc/imx8m/ddr.h>
#include <mach/xload.h>
#include <io.h>
#include <debug_ll.h>
@@ -25,19 +26,11 @@ extern char __dtb_imx8mq_evk_start[];
static void setup_uart(void)
{
- void __iomem *iomux = IOMEM(MX8MQ_IOMUXC_BASE_ADDR);
- void __iomem *ccm = IOMEM(MX8MQ_CCM_BASE_ADDR);
+ imx8m_early_setup_uart_clock();
- writel(CCM_CCGR_SETTINGn_NEEDED(0),
- ccm + CCM_CCGRn_CLR(CCM_CCGR_UART1));
- writel(CCM_TARGET_ROOTn_ENABLE | UART1_CLK_ROOT__25M_REF_CLK,
- ccm + CCM_TARGET_ROOTn(UART1_CLK_ROOT));
- writel(CCM_CCGR_SETTINGn_NEEDED(0),
- ccm + CCM_CCGRn_SET(CCM_CCGR_UART1));
+ imx8mq_setup_pad(IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL);
- imx_setup_pad(iomux, IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL);
-
- imx8_uart_setup_ll();
+ imx8m_uart_setup_ll();
putc_ll('>');
}
@@ -85,9 +78,9 @@ static __noreturn noinline void nxp_imx8mq_evk_start(void)
* for the piggy data, so we need to ensure that we are running
* the same code in DRAM.
*/
- imx8_get_boot_source(&src, &instance);
+ imx8mq_get_boot_source(&src, &instance);
if (src == BOOTSOURCE_MMC)
- ret = imx8_esdhc_load_image(instance, false);
+ ret = imx8m_esdhc_load_image(instance, false);
BUG_ON(ret);
memcpy((void *)MX8MQ_ATF_BL33_BASE_ADDR,
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-512mb.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-512mb.imxcfg
new file mode 100644
index 0000000..5b92e58
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-512mb.imxcfg
@@ -0,0 +1,9 @@
+#define SETUP_MDCFG0 \
+ wm 32 0x021b000c 0x3c409b85
+
+#define SETUP_MDASP_MDCTL \
+ wm 32 0x021b0040 0x00000017; \
+ wm 32 0x021b0000 0x83190000
+
+#include "flash-header-phytec-pcm058dl.h"
+#include <mach/habv4-imx6-gencsf.h>
diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c b/arch/arm/boards/phytec-som-imx6/lowlevel.c
index 900aa19..2e38baa 100644
--- a/arch/arm/boards/phytec-som-imx6/lowlevel.c
+++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c
@@ -111,6 +111,7 @@ PHYTEC_ENTRY(start_phytec_phyboard_subra_1gib_1bank, imx6q_phytec_phyboard_subra
PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_nand_256mb, imx6dl_phytec_phycore_som_nand, SZ_256M, true);
PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_lc_nand_256mb, imx6dl_phytec_phycore_som_lc_nand, SZ_256M, true);
PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_nand_1gib, imx6dl_phytec_phycore_som_nand, SZ_1G, true);
+PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_emmc_512mb, imx6dl_phytec_phycore_som_emmc, SZ_512M, true);
PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_emmc_1gib, imx6dl_phytec_phycore_som_emmc, SZ_1G, true);
PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_lc_emmc_1gib, imx6dl_phytec_phycore_som_lc_emmc, SZ_1G, true);
PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_nand_1gib, imx6q_phytec_phycore_som_nand, SZ_1G, true);
diff --git a/arch/arm/boards/phytec-som-imx8mq/ddr.h b/arch/arm/boards/phytec-som-imx8mq/ddr.h
index 18ae6e9..e125fea 100644
--- a/arch/arm/boards/phytec-som-imx8mq/ddr.h
+++ b/arch/arm/boards/phytec-som-imx8mq/ddr.h
@@ -7,7 +7,7 @@
*/
#include <common.h>
#include <io.h>
-#include <mach/imx8-ddrc.h>
+#include <soc/imx8m/ddr.h>
/*
* Code generated by i.MX8 M DDR Tool doesn't have any prefixes in the
@@ -19,8 +19,3 @@
void phytec_imx8mq_phycore_ddr_init(void);
void phytec_imx8mq_phycore_ddr_cfg_phy(void);
-
-#define FW_1D_IMAGE lpddr4_pmu_train_1d_imem_bin, \
- lpddr4_pmu_train_1d_dmem_bin
-#define FW_2D_IMAGE lpddr4_pmu_train_2d_imem_bin, \
- lpddr4_pmu_train_2d_dmem_bin
diff --git a/arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c b/arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c
index 56af647..cc00527 100644
--- a/arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c
+++ b/arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c
@@ -9,7 +9,6 @@
#include "ddr.h"
-extern void wait_ddrphy_training_complete(void);
void ddr_cfg_phy(void) {
unsigned int tmp, tmp_t;
diff --git a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c
index 4cacabb..f5b9b6c 100644
--- a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c
+++ b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c
@@ -4,13 +4,14 @@
*/
#include <common.h>
+#include <firmware.h>
#include <linux/sizes.h>
#include <mach/generic.h>
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
-#include <mach/imx8-ccm-regs.h>
-#include <mach/iomux-mx8.h>
-#include <mach/imx8-ddrc.h>
+#include <mach/imx8m-ccm-regs.h>
+#include <mach/iomux-mx8mq.h>
+#include <soc/imx8m/ddr.h>
#include <mach/xload.h>
#include <io.h>
#include <debug_ll.h>
@@ -28,19 +29,11 @@ extern char __dtb_imx8mq_phytec_phycore_som_start[];
static void setup_uart(void)
{
- void __iomem *iomux = IOMEM(MX8MQ_IOMUXC_BASE_ADDR);
- void __iomem *ccm = IOMEM(MX8MQ_CCM_BASE_ADDR);
+ imx8m_early_setup_uart_clock();
- writel(CCM_CCGR_SETTINGn_NEEDED(0),
- ccm + CCM_CCGRn_CLR(CCM_CCGR_UART1));
- writel(CCM_TARGET_ROOTn_ENABLE | UART1_CLK_ROOT__25M_REF_CLK,
- ccm + CCM_TARGET_ROOTn(UART1_CLK_ROOT));
- writel(CCM_CCGR_SETTINGn_NEEDED(0),
- ccm + CCM_CCGRn_SET(CCM_CCGR_UART1));
+ imx8mq_setup_pad(IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL);
- imx_setup_pad(iomux, IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL);
-
- imx8_uart_setup_ll();
+ imx8m_uart_setup_ll();
putc_ll('>');
}
@@ -53,10 +46,10 @@ static void phytec_imx8mq_som_sram_setup(void)
ddr_init();
- imx8_get_boot_source(&src, &instance);
+ imx8mq_get_boot_source(&src, &instance);
if (src == BOOTSOURCE_MMC)
- ret = imx8_esdhc_load_image(instance, true);
+ ret = imx8m_esdhc_load_image(instance, true);
BUG_ON(ret);
}
diff --git a/arch/arm/boards/zii-imx7d-dev/lowlevel.c b/arch/arm/boards/zii-imx7d-dev/lowlevel.c
index 3bacfd0..7579a2a 100644
--- a/arch/arm/boards/zii-imx7d-dev/lowlevel.c
+++ b/arch/arm/boards/zii-imx7d-dev/lowlevel.c
@@ -23,17 +23,9 @@ extern char __dtb_z_imx7d_zii_rmu2_start[];
static inline void setup_uart(void)
{
- void __iomem *iomux = IOMEM(MX7_IOMUXC_BASE_ADDR);
- void __iomem *ccm = IOMEM(MX7_CCM_BASE_ADDR);
+ imx7_early_setup_uart_clock();
- writel(CCM_CCGR_SETTINGn_NEEDED(0),
- ccm + CCM_CCGRn_CLR(CCM_CCGR_UART2));
- writel(CCM_TARGET_ROOTn_ENABLE | UART2_CLK_ROOT__OSC_24M,
- ccm + CCM_TARGET_ROOTn(UART2_CLK_ROOT));
- writel(CCM_CCGR_SETTINGn_NEEDED(0),
- ccm + CCM_CCGRn_SET(CCM_CCGR_UART2));
-
- mx7_setup_pad(iomux, MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX);
+ imx7_setup_pad(MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX);
imx7_uart_setup_ll();
diff --git a/arch/arm/boards/zii-imx8mq-dev/ddr.h b/arch/arm/boards/zii-imx8mq-dev/ddr.h
index 1293ad3..a395211 100644
--- a/arch/arm/boards/zii-imx8mq-dev/ddr.h
+++ b/arch/arm/boards/zii-imx8mq-dev/ddr.h
@@ -8,7 +8,7 @@
*/
#include <common.h>
#include <io.h>
-#include <mach/imx8-ddrc.h>
+#include <soc/imx8m/ddr.h>
/*
* Code generated by i.MX8 M DDR Tool doesn't have any prefixes in the
@@ -20,10 +20,3 @@
void zii_imx8mq_rdu3_ddr_init(void);
void zii_imx8mq_rdu3_ddr_cfg_phy(void);
-
-#define FW_1D_IMAGE lpddr4_pmu_train_1d_imem_bin, \
- lpddr4_pmu_train_1d_dmem_bin
-#define FW_2D_IMAGE lpddr4_pmu_train_2d_imem_bin, \
- lpddr4_pmu_train_2d_dmem_bin
-
-
diff --git a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c
index f12d79e..6400833 100644
--- a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c
+++ b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c
@@ -5,13 +5,14 @@
*/
#include <common.h>
+#include <firmware.h>
#include <linux/sizes.h>
#include <mach/generic.h>
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
-#include <mach/imx8-ccm-regs.h>
-#include <mach/iomux-mx8.h>
-#include <mach/imx8-ddrc.h>
+#include <mach/imx8m-ccm-regs.h>
+#include <mach/iomux-mx8mq.h>
+#include <soc/imx8m/ddr.h>
#include <mach/xload.h>
#include <io.h>
#include <debug_ll.h>
@@ -27,19 +28,11 @@
static void setup_uart(void)
{
- void __iomem *iomux = IOMEM(MX8MQ_IOMUXC_BASE_ADDR);
- void __iomem *ccm = IOMEM(MX8MQ_CCM_BASE_ADDR);
+ imx8m_early_setup_uart_clock();
- writel(CCM_CCGR_SETTINGn_NEEDED(0),
- ccm + CCM_CCGRn_CLR(CCM_CCGR_UART1));
- writel(CCM_TARGET_ROOTn_ENABLE | UART1_CLK_ROOT__25M_REF_CLK,
- ccm + CCM_TARGET_ROOTn(UART1_CLK_ROOT));
- writel(CCM_CCGR_SETTINGn_NEEDED(0),
- ccm + CCM_CCGRn_SET(CCM_CCGR_UART1));
+ imx8mq_setup_pad(IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL);
- imx_setup_pad(iomux, IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL);
-
- imx8_uart_setup_ll();
+ imx8m_uart_setup_ll();
putc_ll('>');
}
@@ -75,10 +68,10 @@ static void zii_imx8mq_dev_sram_setup(void)
if (running_as_ddr_helper())
ddr_helper_halt();
- imx8_get_boot_source(&src, &instance);
+ imx8mq_get_boot_source(&src, &instance);
if (src == BOOTSOURCE_MMC)
- ret = imx8_esdhc_load_image(instance, true);
+ ret = imx8m_esdhc_load_image(instance, true);
BUG_ON(ret);
}
diff --git a/arch/arm/configs/imx_v8_defconfig b/arch/arm/configs/imx_v8_defconfig
index 4571ef6..06fb406 100644
--- a/arch/arm/configs/imx_v8_defconfig
+++ b/arch/arm/configs/imx_v8_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARCH_IMX=y
CONFIG_IMX_MULTI_BOARDS=y
CONFIG_MACH_ZII_IMX8MQ_DEV=y
+CONFIG_MACH_NXP_IMX8MM_EVK=y
CONFIG_MACH_NXP_IMX8MQ_EVK=y
CONFIG_MACH_PHYTEC_SOM_IMX8MQ=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
@@ -19,6 +20,7 @@ CONFIG_BOOTM_OFTREE=y
CONFIG_BOOTM_OFTREE_UIMAGE=y
CONFIG_BLSPEC=y
CONFIG_CONSOLE_ACTIVATE_NONE=y
+CONFIG_PBL_CONSOLE=y
CONFIG_CONSOLE_RATP=y
CONFIG_PARTITION_DISK_EFI=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
@@ -70,6 +72,7 @@ CONFIG_CMD_I2C=y
CONFIG_CMD_LED=y
CONFIG_CMD_SPI=y
CONFIG_CMD_LED_TRIGGER=y
+CONFIG_CMD_USBGADGET=y
CONFIG_CMD_WD=y
CONFIG_CMD_BAREBOX_UPDATE=y
CONFIG_CMD_OF_NODE=y
@@ -88,12 +91,22 @@ CONFIG_NET_DSA_MV88E6XXX=y
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_GPIO=y
CONFIG_MDIO_BUS_MUX_GPIO=y
+CONFIG_NET_USB=y
+CONFIG_NET_USB_ASIX=y
+CONFIG_NET_USB_SMSC95XX=y
CONFIG_DRIVER_SPI_IMX=y
CONFIG_I2C=y
CONFIG_I2C_IMX=y
CONFIG_MTD=y
CONFIG_MTD_DATAFLASH=y
CONFIG_MTD_M25P80=y
+CONFIG_USB_HOST=y
+CONFIG_USB_IMX_CHIPIDEA=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_SERIAL=y
+CONFIG_USB_GADGET_FASTBOOT=y
+CONFIG_USB_GADGET_FASTBOOT_SPARSE=y
CONFIG_MCI=y
CONFIG_MCI_MMC_BOOT_PARTITIONS=y
CONFIG_MCI_IMX_ESDHC=y
@@ -107,13 +120,15 @@ CONFIG_EEPROM_AT24=y
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_IMX=y
CONFIG_RAVE_SP_WATCHDOG=y
-CONFIG_NVMEM=y
CONFIG_IMX_OCOTP=y
CONFIG_RAVE_SP_EEPROM=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_DS1307=y
+CONFIG_GENERIC_PHY=y
+CONFIG_USB_NOP_XCEIV=y
+CONFIG_PHY_FSL_IMX8MQ_USB=y
CONFIG_FS_EXT4=y
CONFIG_FS_TFTP=y
CONFIG_FS_NFS=y
@@ -122,4 +137,3 @@ CONFIG_FS_FAT_WRITE=y
CONFIG_FS_FAT_LFN=y
CONFIG_FS_RATP=y
CONFIG_ZLIB=y
-CONFIG_LZO_DECOMPRESS=y
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 20eafb6..ddfe64e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -98,6 +98,7 @@ lwl-dtb-$(CONFIG_MACH_SCB9328) += imx1-scb9328.dtb.o
lwl-dtb-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += imx6q-wandboard.dtb.o imx6dl-wandboard.dtb.o
lwl-dtb-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += imx6ul-pico-hobbit.dtb.o
lwl-dtb-$(CONFIG_MACH_NXP_IMX6ULL_EVK) += imx6ull-14x14-evk.dtb.o
+lwl-dtb-$(CONFIG_MACH_NXP_IMX8MM_EVK) += imx8mm-evk.dtb.o
lwl-dtb-$(CONFIG_MACH_NXP_IMX8MQ_EVK) += imx8mq-evk.dtb.o
lwl-dtb-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += tegra20-colibri-iris.dtb.o
lwl-dtb-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o
diff --git a/arch/arm/dts/imx51-genesi-efika-sb.dts b/arch/arm/dts/imx51-genesi-efika-sb.dts
index da6b6f9..23e6ea4 100644
--- a/arch/arm/dts/imx51-genesi-efika-sb.dts
+++ b/arch/arm/dts/imx51-genesi-efika-sb.dts
@@ -345,7 +345,7 @@
clock-frequency = <100000>;
status = "okay";
- sgtl5000: codec@0a {
+ sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clock-frequency = <12288000>;
@@ -354,7 +354,7 @@
VDDIO-supply = <&vvideo_reg>;
};
- battery: battery@0b {
+ battery: battery@b {
compatible = "sbs,sbs-battery";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_battery>;
@@ -526,7 +526,7 @@
};
};
- flash: m25p80 {
+ flash: m25p80@1 {
compatible = "sst,sst25vf032b", "m25p80";
spi-max-frequency = <15000000>;
reg = <1>;
diff --git a/arch/arm/dts/imx53-guf-vincell-lt.dts b/arch/arm/dts/imx53-guf-vincell-lt.dts
index 7a133a5..4c62051 100644
--- a/arch/arm/dts/imx53-guf-vincell-lt.dts
+++ b/arch/arm/dts/imx53-guf-vincell-lt.dts
@@ -146,7 +146,7 @@
bitrate = <100000>;
status = "okay";
- sgtl5000: codec@0a {
+ sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
};
diff --git a/arch/arm/dts/imx6dl-advantech-rom-7421.dts b/arch/arm/dts/imx6dl-advantech-rom-7421.dts
index cdf3781..f0e3f4a 100755
--- a/arch/arm/dts/imx6dl-advantech-rom-7421.dts
+++ b/arch/arm/dts/imx6dl-advantech-rom-7421.dts
@@ -86,6 +86,10 @@
status = "okay";
};
+&ocotp {
+ barebox,provide-mac-address = <&fec 0x620>;
+};
+
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
@@ -100,7 +104,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <8>;
- cd-gpios = <&gpio2 0 0>;
+ cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
status = "okay";
#address-cells = <1>;
@@ -121,9 +125,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
bus-width = <4>;
- cd-gpios = <&gpio2 1 0>;
- en-gpios = <&gpio2 2 0>;
- wp-gpios = <&gpio2 3 0>;
+ cd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+ en-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
status = "okay";
};
diff --git a/arch/arm/dts/imx6dl-eltec-hipercam.dts b/arch/arm/dts/imx6dl-eltec-hipercam.dts
index fe33604..41af229 100644
--- a/arch/arm/dts/imx6dl-eltec-hipercam.dts
+++ b/arch/arm/dts/imx6dl-eltec-hipercam.dts
@@ -91,13 +91,13 @@
pinctrl-names = "default";
pinctrl-0 = <0x20>;
- eeprom@0x52 {
+ eeprom@52 {
compatible = "amtel,24c04";
reg = <0x52>;
pagesize = <0x10>;
};
- pfuze100@08 {
+ pfuze100@8 {
compatible = "fsl,pfuze100";
reg = <0x8>;
diff --git a/arch/arm/dts/imx6q-guf-santaro.dts b/arch/arm/dts/imx6q-guf-santaro.dts
index 8f886c4..0fb05d0 100644
--- a/arch/arm/dts/imx6q-guf-santaro.dts
+++ b/arch/arm/dts/imx6q-guf-santaro.dts
@@ -93,7 +93,7 @@
reg = <0x50>;
};
- pmic: pf0100@08 {
+ pmic: pf0100@8 {
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
@@ -195,7 +195,7 @@
};
};
- codec: sgtl5000@0a {
+ codec: sgtl5000@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clks 201>;
diff --git a/arch/arm/dts/imx6qdl-cm-fx6.dtsi b/arch/arm/dts/imx6qdl-cm-fx6.dtsi
index 72d00f1..3082acb 100644
--- a/arch/arm/dts/imx6qdl-cm-fx6.dtsi
+++ b/arch/arm/dts/imx6qdl-cm-fx6.dtsi
@@ -363,6 +363,8 @@
/* nand */
&gpmi {
+ #address-cells = <1>;
+ #size-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
status = "okay";
diff --git a/arch/arm/dts/imx6qdl-hummingboard2.dtsi b/arch/arm/dts/imx6qdl-hummingboard2.dtsi
index 2015224..6f37d5a 100644
--- a/arch/arm/dts/imx6qdl-hummingboard2.dtsi
+++ b/arch/arm/dts/imx6qdl-hummingboard2.dtsi
@@ -173,7 +173,7 @@
reg = <0x68>;
};
- sgtl5000: codec@0a {
+ sgtl5000: codec@a {
clocks = <&clks IMX6QDL_CLK_CKO>;
compatible = "fsl,sgtl5000";
pinctrl-names = "default";
diff --git a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
index 918b62f..e99846c 100644
--- a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
@@ -29,7 +29,7 @@
environment-spinor {
compatible = "barebox,environment";
- device-path = &m25p80, "partname:barebox-environment";
+ device-path = &m25p80, "partname:nor.barebox-environment";
status = "disabled";
};
};
@@ -86,22 +86,22 @@
#size-cells = <1>;
partition@0 {
- label = "barebox";
+ label = "nor.barebox";
reg = <0x0 0x100000>;
};
partition@100000 {
- label = "barebox-environment";
+ label = "nor.barebox-environment";
reg = <0x100000 0x20000>;
};
partition@120000 {
- label = "oftree";
+ label = "nor.oftree";
reg = <0x120000 0x20000>;
};
partition@140000 {
- label = "kernel";
+ label = "nor.kernel";
reg = <0x140000 0x0>;
};
};
diff --git a/arch/arm/dts/imx6qdl-tqma6x.dtsi b/arch/arm/dts/imx6qdl-tqma6x.dtsi
index 82f9ec3..3bcd7eb 100644
--- a/arch/arm/dts/imx6qdl-tqma6x.dtsi
+++ b/arch/arm/dts/imx6qdl-tqma6x.dtsi
@@ -108,7 +108,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
- pmic: pf0100@08 {
+ pmic: pf0100@8 {
compatible = "pf0100-regulator";
reg = <0x08>;
interrupt-parent = <&gpio6>;
diff --git a/arch/arm/dts/imx6qdl-tx6x.dtsi b/arch/arm/dts/imx6qdl-tx6x.dtsi
index ef0f935..1310216 100644
--- a/arch/arm/dts/imx6qdl-tx6x.dtsi
+++ b/arch/arm/dts/imx6qdl-tx6x.dtsi
@@ -25,6 +25,8 @@
};
&gpmi {
+ #address-cells = <1>;
+ #size-cells = <1>;
status = "disabled";
partition@0 {
diff --git a/arch/arm/dts/imx7d-phycore-som.dtsi b/arch/arm/dts/imx7d-phycore-som.dtsi
index ea8c801..622261b 100644
--- a/arch/arm/dts/imx7d-phycore-som.dtsi
+++ b/arch/arm/dts/imx7d-phycore-som.dtsi
@@ -28,7 +28,7 @@
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
- pmic: pfuze3000@08 {
+ pmic: pfuze3000@8 {
compatible = "fsl,pfuze3000";
reg = <0x08>;
diff --git a/arch/arm/dts/imx8mm-evk.dts b/arch/arm/dts/imx8mm-evk.dts
new file mode 100644
index 0000000..1e8619c
--- /dev/null
+++ b/arch/arm/dts/imx8mm-evk.dts
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2017 NXP
+ * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
+ */
+
+/dts-v1/;
+
+#include <arm64/freescale/imx8mm-evk.dts>
+
+/ {
+ chosen {
+ environment-sd {
+ compatible = "barebox,environment";
+ device-path = &usdhc2, "partname:barebox-environment";
+ status = "disabled";
+ };
+ environment-emmc {
+ compatible = "barebox,environment";
+ device-path = &usdhc3, "partname:barebox-environment";
+ status = "disabled";
+ };
+ };
+};
+
+&fec1 {
+ phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+};
+
+&usdhc2 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "barebox";
+ reg = <0x0 0xe0000>;
+ };
+
+ partition@e0000 {
+ label = "barebox-environment";
+ reg = <0xe0000 0x20000>;
+ };
+};
+
+&usdhc3 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "barebox";
+ reg = <0x0 0xe0000>;
+ };
+
+ partition@e0000 {
+ label = "barebox-environment";
+ reg = <0xe0000 0x20000>;
+ };
+};
+
+&ocotp {
+ barebox,provide-mac-address = <&fec1 0x640>;
+};
diff --git a/arch/arm/dts/vf610-zii-scu4-aib.dts b/arch/arm/dts/vf610-zii-scu4-aib.dts
index 1e6a549..43a13e2 100644
--- a/arch/arm/dts/vf610-zii-scu4-aib.dts
+++ b/arch/arm/dts/vf610-zii-scu4-aib.dts
@@ -109,11 +109,3 @@
label = "fiber9";
};
};
-
-/*
- * FIXME: Remove once this code appears in kernel DTS
-*/
-&i2c2 {
- tca9548@70 { i2c-mux-idle-disconnect; };
- tca9548@71 { i2c-mux-idle-disconnect; };
-};
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index f5c8a42..116761b 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -174,7 +174,7 @@ config ARCH_IMX7
select ARCH_HAS_IMX_GPT
select HW_HAS_PCI
-config ARCH_IMX8MQ
+config ARCH_IMX8M
bool
select CPU_V8
select PINCTRL_IMX_IOMUX_V3
@@ -183,8 +183,17 @@ config ARCH_IMX8MQ
select COMMON_CLK_OF_PROVIDER
select ARCH_HAS_FEC_IMX
select HW_HAS_PCI
+ select IMX8M_DRAM
select PBL_VERIFY_PIGGY if HABV4
+config ARCH_IMX8MM
+ select ARCH_IMX8M
+ bool
+
+config ARCH_IMX8MQ
+ select ARCH_IMX8M
+ bool
+
config ARCH_VF610
bool
select ARCH_HAS_L2X0
@@ -502,6 +511,16 @@ config MACH_NXP_IMX6ULL_EVK
bool "NXP i.MX6ull EVK Board"
select ARCH_IMX6UL
+config MACH_NXP_IMX8MM_EVK
+ bool "NXP i.MX8MM EVK Board"
+ select ARCH_IMX8MM
+ select FIRMWARE_IMX8MM_ATF
+ select ARM_SMCCC
+ select MCI_IMX_ESDHC_PBL
+ select IMX8M_DRAM
+ select I2C_IMX_EARLY
+ select USB_GADGET_DRIVER_ARC_PBL
+
config MACH_NXP_IMX8MQ_EVK
bool "NXP i.MX8MQ EVK Board"
select ARCH_IMX8MQ
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index fae81e1..e45f758 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -15,8 +15,8 @@ CFLAGS_imx6.o := -march=armv7-a
lwl-$(CONFIG_ARCH_IMX6) += imx6-mmdc.o
obj-$(CONFIG_ARCH_IMX7) += imx7.o
obj-$(CONFIG_ARCH_VF610) += vf610.o
-obj-$(CONFIG_ARCH_IMX8MQ) += imx8mq.o
-lwl-$(CONFIG_ARCH_IMX8MQ) += imx8-ddrc.o atf.o
+obj-pbl-$(CONFIG_ARCH_IMX8M) += imx8m.o
+lwl-$(CONFIG_ARCH_IMX8M) += atf.o
obj-$(CONFIG_IMX_IIM) += iim.o
obj-$(CONFIG_NAND_IMX) += nand.o
lwl-$(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND) += external-nand-boot.o
diff --git a/arch/arm/mach-imx/atf.c b/arch/arm/mach-imx/atf.c
index c1b358d..4ced8cd 100644
--- a/arch/arm/mach-imx/atf.c
+++ b/arch/arm/mach-imx/atf.c
@@ -2,13 +2,14 @@
#include <mach/atf.h>
/**
- * imx8mq_atf_load_bl31 - Load ATF BL31 blob and transfer control to it
+ * imx8m_atf_load_bl31 - Load ATF BL31 blob and transfer control to it
*
* @fw: Pointer to the BL31 blob
* @fw_size: Size of the BL31 blob
+ * @atf_dest: Place where the BL31 is copied to and executed
*
* This function:
-
+ *
* 1. Copies built-in BL31 blob to an address i.MX8M's BL31
* expects to be placed
*
@@ -25,17 +26,28 @@
* any other implementation may or may not work
*
*/
-void imx8mq_atf_load_bl31(const void *fw, size_t fw_size)
+
+static void imx8m_atf_load_bl31(const void *fw, size_t fw_size, void *atf_dest)
{
- void __noreturn (*bl31)(void) = (void *)MX8MQ_ATF_BL31_BASE_ADDR;
+ void __noreturn (*bl31)(void) = atf_dest;
- if (WARN_ON(fw_size > MX8MQ_ATF_BL31_SIZE_LIMIT))
+ if (WARN_ON(fw_size > MX8M_ATF_BL31_SIZE_LIMIT))
return;
memcpy(bl31, fw, fw_size);
asm volatile("msr sp_el2, %0" : :
- "r" (MX8MQ_ATF_BL33_BASE_ADDR - 16) :
+ "r" (atf_dest - 16) :
"cc");
bl31();
-} \ No newline at end of file
+}
+
+void imx8mm_atf_load_bl31(const void *fw, size_t fw_size)
+{
+ imx8m_atf_load_bl31(fw, fw_size, (void *)MX8MM_ATF_BL31_BASE_ADDR);
+}
+
+void imx8mq_atf_load_bl31(const void *fw, size_t fw_size)
+{
+ imx8m_atf_load_bl31(fw, fw_size, (void *)MX8MQ_ATF_BL31_BASE_ADDR);
+}
diff --git a/arch/arm/mach-imx/boot.c b/arch/arm/mach-imx/boot.c
index 0c51767..7bce1c7 100644
--- a/arch/arm/mach-imx/boot.c
+++ b/arch/arm/mach-imx/boot.c
@@ -27,6 +27,8 @@
#include <mach/imx53-regs.h>
#include <mach/imx6-regs.h>
#include <mach/imx7-regs.h>
+#include <mach/imx8mm-regs.h>
+#include <mach/imx8mq-regs.h>
#include <mach/vf610-regs.h>
#include <mach/imx8mq.h>
@@ -444,10 +446,16 @@ struct imx_boot_sw_info {
} __packed;
static void __imx7_get_boot_source(enum bootsource *src, int *instance,
- unsigned long boot_sw_info_pointer_addr)
+ unsigned long boot_sw_info_pointer_addr,
+ uint32_t sbmr2)
{
const struct imx_boot_sw_info *info;
+ if (imx6_bootsource_serial(sbmr2)) {
+ *src = BOOTSOURCE_SERIAL;
+ return;
+ }
+
info = (const void *)(unsigned long)
readl(boot_sw_info_pointer_addr);
@@ -477,7 +485,11 @@ static void __imx7_get_boot_source(enum bootsource *src, int *instance,
void imx7_get_boot_source(enum bootsource *src, int *instance)
{
- __imx7_get_boot_source(src, instance, IMX7_BOOT_SW_INFO_POINTER_ADDR);
+ void __iomem *src_base = IOMEM(MX7_SRC_BASE_ADDR);
+ uint32_t sbmr2 = readl(src_base + 0x70);
+
+ __imx7_get_boot_source(src, instance, IMX7_BOOT_SW_INFO_POINTER_ADDR,
+ sbmr2);
}
void imx7_boot_save_loc(void)
@@ -579,18 +591,36 @@ void vf610_boot_save_loc(void)
imx_boot_save_loc(vf610_get_boot_source);
}
-void imx8_get_boot_source(enum bootsource *src, int *instance)
+void imx8mq_get_boot_source(enum bootsource *src, int *instance)
{
unsigned long addr;
+ void __iomem *src_base = IOMEM(MX8M_SRC_BASE_ADDR);
+ uint32_t sbmr2 = readl(src_base + 0x70);
addr = (imx8mq_cpu_revision() == IMX_CHIP_REV_1_0) ?
IMX8M_BOOT_SW_INFO_POINTER_ADDR_A0 :
IMX8M_BOOT_SW_INFO_POINTER_ADDR_B0;
- __imx7_get_boot_source(src, instance, addr);
+ __imx7_get_boot_source(src, instance, addr, sbmr2);
+}
+
+void imx8mq_boot_save_loc(void)
+{
+ imx_boot_save_loc(imx8mq_get_boot_source);
+}
+
+void imx8mm_get_boot_source(enum bootsource *src, int *instance)
+{
+ unsigned long addr;
+ void __iomem *src_base = IOMEM(MX8MM_SRC_BASE_ADDR);
+ uint32_t sbmr2 = readl(src_base + 0x70);
+
+ addr = IMX8M_BOOT_SW_INFO_POINTER_ADDR_A0;
+
+ __imx7_get_boot_source(src, instance, addr, sbmr2);
}
-void imx8_boot_save_loc(void)
+void imx8mm_boot_save_loc(void)
{
- imx_boot_save_loc(imx8_get_boot_source);
+ imx_boot_save_loc(imx8mm_get_boot_source);
}
diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c
index aa6e050..c6a0ac7 100644
--- a/arch/arm/mach-imx/cpu_init.c
+++ b/arch/arm/mach-imx/cpu_init.c
@@ -69,11 +69,21 @@ void vf610_cpu_lowlevel_init(void)
arm_cpu_lowlevel_init();
}
#else
-void imx8mq_cpu_lowlevel_init(void)
+static void imx8m_cpu_lowlevel_init(void)
{
arm_cpu_lowlevel_init();
if (current_el() == 3)
- imx_cpu_timer_init(IOMEM(MX8MQ_SYSCNT_CTRL_BASE_ADDR));
+ imx_cpu_timer_init(IOMEM(MX8M_SYSCNT_CTRL_BASE_ADDR));
+}
+
+void imx8mm_cpu_lowlevel_init(void)
+{
+ imx8m_cpu_lowlevel_init();
+}
+
+void imx8mq_cpu_lowlevel_init(void)
+{
+ imx8m_cpu_lowlevel_init();
}
#endif
diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
index 074e3ac..25e7c83 100644
--- a/arch/arm/mach-imx/esdctl.c
+++ b/arch/arm/mach-imx/esdctl.c
@@ -39,7 +39,7 @@
#include <mach/imx53-regs.h>
#include <mach/imx6-regs.h>
#include <mach/vf610-ddrmc.h>
-#include <mach/imx8mq-regs.h>
+#include <mach/imx8m-regs.h>
#include <mach/imx7-regs.h>
struct imx_esdctl_data {
@@ -428,7 +428,7 @@ imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[],
return reduced_adress_space ? size * 3 / 4 : size;
}
-static resource_size_t imx8mq_ddrc_sdram_size(void __iomem *ddrc)
+static resource_size_t imx8m_ddrc_sdram_size(void __iomem *ddrc)
{
const u32 addrmap[] = {
readl(ddrc + DDRC_ADDRMAP(0)),
@@ -480,10 +480,10 @@ static resource_size_t imx8mq_ddrc_sdram_size(void __iomem *ddrc)
reduced_adress_space);
}
-static void imx8mq_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
+static void imx8m_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
{
arm_add_mem_device("ram0", data->base0,
- imx8mq_ddrc_sdram_size(mmdcbase));
+ imx8m_ddrc_sdram_size(mmdcbase));
}
static resource_size_t imx7d_ddrc_sdram_size(void __iomem *ddrc)
@@ -615,8 +615,8 @@ static __maybe_unused struct imx_esdctl_data vf610_data = {
};
static __maybe_unused struct imx_esdctl_data imx8mq_data = {
- .base0 = MX8MQ_DDR_CSD1_BASE_ADDR,
- .add_mem = imx8mq_ddrc_add_mem,
+ .base0 = MX8M_DDR_CSD1_BASE_ADDR,
+ .add_mem = imx8m_ddrc_add_mem,
};
static __maybe_unused struct imx_esdctl_data imx7d_data = {
@@ -869,11 +869,11 @@ void __noreturn vf610_barebox_entry(void *boarddata)
boarddata);
}
-void __noreturn imx8mq_barebox_entry(void *boarddata)
+static void __noreturn imx8m_barebox_entry(void *boarddata)
{
resource_size_t size;
- size = imx8mq_ddrc_sdram_size(IOMEM(MX8MQ_DDRC_CTL_BASE_ADDR));
+ size = imx8m_ddrc_sdram_size(IOMEM(MX8M_DDRC_CTL_BASE_ADDR));
/*
* We artificially limit detected memory size to force malloc
* pool placement to be within 4GiB address space, so as to
@@ -883,8 +883,18 @@ void __noreturn imx8mq_barebox_entry(void *boarddata)
* pool placement. The rest of the system should be able to
* detect and utilize full amount of memory.
*/
- size = min_t(resource_size_t, SZ_4G - MX8MQ_DDR_CSD1_BASE_ADDR, size);
- barebox_arm_entry(MX8MQ_DDR_CSD1_BASE_ADDR, size, boarddata);
+ size = min_t(resource_size_t, SZ_4G - MX8M_DDR_CSD1_BASE_ADDR, size);
+ barebox_arm_entry(MX8M_DDR_CSD1_BASE_ADDR, size, boarddata);
+}
+
+void __noreturn imx8mm_barebox_entry(void *boarddata)
+{
+ imx8m_barebox_entry(boarddata);
+}
+
+void __noreturn imx8mq_barebox_entry(void *boarddata)
+{
+ imx8m_barebox_entry(boarddata);
}
void __noreturn imx7d_barebox_entry(void *boarddata)
diff --git a/arch/arm/mach-imx/imx-bbu-internal.c b/arch/arm/mach-imx/imx-bbu-internal.c
index 946a3e9..f6f6636 100644
--- a/arch/arm/mach-imx/imx-bbu-internal.c
+++ b/arch/arm/mach-imx/imx-bbu-internal.c
@@ -375,7 +375,7 @@ out:
static enum filetype imx_bbu_expected_filetype(void)
{
- if (cpu_is_mx8mq() ||
+ if (cpu_is_mx8m() ||
cpu_is_mx7() ||
cpu_is_mx6() ||
cpu_is_vf610() ||
@@ -393,7 +393,7 @@ static unsigned long imx_bbu_flash_header_offset_mmc(void)
* i.MX8MQ moved the header by 32K to accomodate for GPT
* partition tables
*/
- if (cpu_is_mx8mq())
+ if (cpu_is_mx8m())
offset += SZ_32K;
return offset;
diff --git a/arch/arm/mach-imx/imx.c b/arch/arm/mach-imx/imx.c
index 0942d50..ca2e77b 100644
--- a/arch/arm/mach-imx/imx.c
+++ b/arch/arm/mach-imx/imx.c
@@ -80,6 +80,8 @@ static int imx_soc_from_dt(void)
return IMX_CPU_IMX7;
if (of_machine_is_compatible("fsl,imx8mq"))
return IMX_CPU_IMX8MQ;
+ if (of_machine_is_compatible("fsl,imx8mm"))
+ return IMX_CPU_IMX8MM;
if (of_machine_is_compatible("fsl,vf610"))
return IMX_CPU_VF610;
@@ -120,6 +122,8 @@ static int imx_init(void)
ret = imx6_init();
else if (cpu_is_mx7())
ret = imx7_init();
+ else if (cpu_is_mx8mm())
+ ret = imx8mm_init();
else if (cpu_is_mx8mq())
ret = imx8mq_init();
else if (cpu_is_vf610())
diff --git a/arch/arm/mach-imx/imx8-ddrc.c b/arch/arm/mach-imx/imx8-ddrc.c
deleted file mode 100644
index 8bb2672..0000000
--- a/arch/arm/mach-imx/imx8-ddrc.c
+++ /dev/null
@@ -1,91 +0,0 @@
-#include <common.h>
-#include <linux/iopoll.h>
-#include <mach/imx8-ddrc.h>
-#include <debug_ll.h>
-
-void ddrc_phy_load_firmware(void __iomem *phy,
- enum ddrc_phy_firmware_offset offset,
- const u16 *blob, size_t size)
-{
- while (size) {
- writew(*blob++, phy + DDRC_PHY_REG(offset));
- offset++;
- size -= sizeof(*blob);
- }
-}
-
-enum pmc_constants {
- PMC_MESSAGE_ID,
- PMC_MESSAGE_STREAM,
-
- PMC_TRAIN_SUCCESS = 0x07,
- PMC_TRAIN_STREAM_START = 0x08,
- PMC_TRAIN_FAIL = 0xff,
-};
-
-static u32 ddrc_phy_get_message(void __iomem *phy, int type)
-{
- u32 r, message;
-
- /*
- * When BIT0 set to 0, the PMU has a message for the user
- * Wait for it indefinitely.
- */
- readl_poll_timeout(phy + DDRC_PHY_REG(0xd0004),
- r, !(r & BIT(0)), 0);
-
- switch (type) {
- case PMC_MESSAGE_ID:
- /*
- * Get the major message ID
- */
- message = readl(phy + DDRC_PHY_REG(0xd0032));
- break;
- case PMC_MESSAGE_STREAM:
- message = readl(phy + DDRC_PHY_REG(0xd0034));
- message <<= 16;
- message |= readl(phy + DDRC_PHY_REG(0xd0032));
- break;
- }
-
- /*
- * By setting this register to 0, the user acknowledges the
- * receipt of the message.
- */
- writel(0x00000000, phy + DDRC_PHY_REG(0xd0031));
- /*
- * When BIT0 set to 0, the PMU has a message for the user
- */
- readl_poll_timeout(phy + DDRC_PHY_REG(0xd0004),
- r, r & BIT(0), 0);
-
- writel(0x00000001, phy + DDRC_PHY_REG(0xd0031));
-
- return message;
-}
-
-static void ddrc_phy_fetch_streaming_message(void __iomem *phy)
-{
- const u16 index = ddrc_phy_get_message(phy, PMC_MESSAGE_STREAM);
- u16 i;
-
- for (i = 0; i < index; i++)
- ddrc_phy_get_message(phy, PMC_MESSAGE_STREAM);
-}
-
-void ddrc_phy_wait_training_complete(void __iomem *phy)
-{
- for (;;) {
- const u32 m = ddrc_phy_get_message(phy, PMC_MESSAGE_ID);
-
- switch (m) {
- case PMC_TRAIN_STREAM_START:
- ddrc_phy_fetch_streaming_message(phy);
- break;
- case PMC_TRAIN_SUCCESS:
- return;
- case PMC_TRAIN_FAIL:
- hang();
- }
- }
-}
diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c
new file mode 100644
index 0000000..d2ed7d5
--- /dev/null
+++ b/arch/arm/mach-imx/imx8m.c
@@ -0,0 +1,279 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <init.h>
+#include <common.h>
+#include <io.h>
+#include <asm/syscounter.h>
+#include <asm/system.h>
+#include <mach/generic.h>
+#include <mach/revision.h>
+#include <mach/imx8mq.h>
+#include <mach/imx8m-ccm-regs.h>
+#include <mach/reset-reason.h>
+#include <mach/ocotp.h>
+#include <mach/imx8mq-regs.h>
+#include <mach/imx8m-ccm-regs.h>
+#include <soc/imx8m/clk-early.h>
+
+#include <linux/iopoll.h>
+#include <linux/arm-smccc.h>
+
+#define FSL_SIP_BUILDINFO 0xC2000003
+#define FSL_SIP_BUILDINFO_GET_COMMITHASH 0x00
+
+void imx8m_clock_set_target_val(int clock_id, u32 val)
+{
+ void *ccm = IOMEM(MX8M_CCM_BASE_ADDR);
+
+ writel(val, ccm + IMX8M_CCM_TARGET_ROOTn(clock_id));
+}
+
+void imx8m_ccgr_clock_enable(int index)
+{
+ void *ccm = IOMEM(MX8M_CCM_BASE_ADDR);
+
+ writel(IMX8M_CCM_CCGR_SETTINGn_NEEDED(0),
+ ccm + IMX8M_CCM_CCGRn_SET(index));
+}
+
+void imx8m_ccgr_clock_disable(int index)
+{
+ void *ccm = IOMEM(MX8M_CCM_BASE_ADDR);
+
+ writel(IMX8M_CCM_CCGR_SETTINGn_NEEDED(0),
+ ccm + IMX8M_CCM_CCGRn_CLR(index));
+}
+
+u64 imx8m_uid(void)
+{
+ return imx_ocotp_read_uid(IOMEM(MX8M_OCOTP_BASE_ADDR));
+}
+
+static int imx8m_init(const char *cputypestr)
+{
+ void __iomem *src = IOMEM(MX8M_SRC_BASE_ADDR);
+ struct arm_smccc_res res;
+
+ /*
+ * Reset reasons seem to be identical to that of i.MX7
+ */
+ imx_set_reset_reason(src + IMX7_SRC_SRSR, imx7_reset_reasons);
+ pr_info("%s unique ID: %llx\n", cputypestr, imx8m_uid());
+
+ if (IS_ENABLED(CONFIG_ARM_SMCCC) &&
+ IS_ENABLED(CONFIG_FIRMWARE_IMX8MQ_ATF)) {
+ arm_smccc_smc(FSL_SIP_BUILDINFO,
+ FSL_SIP_BUILDINFO_GET_COMMITHASH,
+ 0, 0, 0, 0, 0, 0, &res);
+ pr_info("i.MX ARM Trusted Firmware: %s\n", (char *)&res.a0);
+ }
+
+ return 0;
+}
+
+int imx8mm_init(void)
+{
+ void __iomem *anatop = IOMEM(MX8M_ANATOP_BASE_ADDR);
+ uint32_t type = FIELD_GET(DIGPROG_MAJOR,
+ readl(anatop + MX8MM_ANATOP_DIGPROG));
+ const char *cputypestr;
+
+ imx8mm_boot_save_loc();
+
+ switch (type) {
+ case IMX8M_CPUTYPE_IMX8MM:
+ cputypestr = "i.MX8MM";
+ break;
+ default:
+ cputypestr = "unknown i.MX8M";
+ break;
+ };
+
+ imx_set_silicon_revision(cputypestr, imx8mm_cpu_revision());
+
+ return imx8m_init(cputypestr);
+}
+
+int imx8mq_init(void)
+{
+ void __iomem *anatop = IOMEM(MX8M_ANATOP_BASE_ADDR);
+ uint32_t type = FIELD_GET(DIGPROG_MAJOR,
+ readl(anatop + MX8MQ_ANATOP_DIGPROG));
+ const char *cputypestr;
+
+ imx8mq_boot_save_loc();
+
+ switch (type) {
+ case IMX8M_CPUTYPE_IMX8MQ:
+ cputypestr = "i.MX8MQ";
+ break;
+ default:
+ cputypestr = "unknown i.MX8M";
+ break;
+ };
+
+ imx_set_silicon_revision(cputypestr, imx8mq_cpu_revision());
+
+ return imx8m_init(cputypestr);
+}
+
+#define INTPLL_DIV20_CLKE_MASK BIT(27)
+#define INTPLL_DIV10_CLKE_MASK BIT(25)
+#define INTPLL_DIV8_CLKE_MASK BIT(23)
+#define INTPLL_DIV6_CLKE_MASK BIT(21)
+#define INTPLL_DIV5_CLKE_MASK BIT(19)
+#define INTPLL_DIV4_CLKE_MASK BIT(17)
+#define INTPLL_DIV3_CLKE_MASK BIT(15)
+#define INTPLL_DIV2_CLKE_MASK BIT(13)
+#define INTPLL_CLKE_MASK BIT(11)
+
+#define CCM_TARGET_ROOT0_DIV GENMASK(1, 0)
+
+#define IMX8MM_CCM_ANALOG_ARM_PLL_GEN_CTRL 0x84
+#define IMX8MM_CCM_ANALOG_SYS_PLL1_GEN_CTRL 0x94
+#define IMX8MM_CCM_ANALOG_SYS_PLL2_GEN_CTRL 0x104
+#define IMX8MM_CCM_ANALOG_SYS_PLL3_GEN_CTRL 0x114
+
+void imx8mm_early_clock_init(void)
+{
+ void __iomem *ana = IOMEM(MX8M_ANATOP_BASE_ADDR);
+ void __iomem *ccm = IOMEM(MX8M_CCM_BASE_ADDR);
+ u32 val;
+
+ imx8m_ccgr_clock_disable(IMX8M_CCM_CCGR_DDR1);
+
+ imx8m_clock_set_target_val(IMX8M_DRAM_ALT_CLK_ROOT,
+ IMX8M_CCM_TARGET_ROOTn_ENABLE |
+ IMX8M_CCM_TARGET_ROOTn_MUX(1));
+
+ /* change the clock source of dram_apb_clk_root: source 4 800MHz /4 = 200MHz */
+ imx8m_clock_set_target_val(IMX8M_DRAM_APB_CLK_ROOT,
+ IMX8M_CCM_TARGET_ROOTn_ENABLE |
+ IMX8M_CCM_TARGET_ROOTn_MUX(4) |
+ IMX8M_CCM_TARGET_ROOTn_POST_DIV(4 - 1));
+
+ imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_DDR1);
+
+ val = readl(ana + IMX8MM_CCM_ANALOG_SYS_PLL1_GEN_CTRL);
+ val |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
+ INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
+ INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
+ INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
+ INTPLL_DIV20_CLKE_MASK;
+ writel(val, ana + IMX8MM_CCM_ANALOG_SYS_PLL1_GEN_CTRL);
+
+ val = readl(ana + IMX8MM_CCM_ANALOG_SYS_PLL2_GEN_CTRL);
+ val |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
+ INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
+ INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
+ INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
+ INTPLL_DIV20_CLKE_MASK;
+ writel(val, ana + IMX8MM_CCM_ANALOG_SYS_PLL2_GEN_CTRL);
+
+ /* config GIC to sys_pll2_100m */
+ imx8m_ccgr_clock_disable(IMX8M_CCM_CCGR_GIC);
+ imx8m_clock_set_target_val(IMX8M_GIC_CLK_ROOT,
+ IMX8M_CCM_TARGET_ROOTn_ENABLE |
+ IMX8M_CCM_TARGET_ROOTn_MUX(3));
+ imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_GIC);
+
+ /* Configure SYS_PLL3 to 750MHz */
+ clk_pll1416x_early_set_rate(ana + IMX8MM_CCM_ANALOG_SYS_PLL3_GEN_CTRL,
+ 750000000UL, 25000000UL);
+
+ clrsetbits_le32(ccm + IMX8M_CCM_TARGET_ROOTn(IMX8M_ARM_A53_CLK_ROOT),
+ IMX8M_CCM_TARGET_ROOTn_MUX(7),
+ IMX8M_CCM_TARGET_ROOTn_MUX(2));
+
+ /* Configure ARM PLL to 1.2GHz */
+ clk_pll1416x_early_set_rate(ana + IMX8MM_CCM_ANALOG_ARM_PLL_GEN_CTRL,
+ 1200000000UL, 25000000UL);
+
+ clrsetbits_le32(ana + IMX8MM_CCM_ANALOG_ARM_PLL_GEN_CTRL, 0,
+ INTPLL_CLKE_MASK);
+
+ clrsetbits_le32(ccm + IMX8M_CCM_TARGET_ROOTn(IMX8M_ARM_A53_CLK_ROOT),
+ IMX8M_CCM_TARGET_ROOTn_MUX(7),
+ IMX8M_CCM_TARGET_ROOTn_MUX(1));
+
+ /* Configure DIV to 1.2GHz */
+ clrsetbits_le32(ccm + IMX8M_CCM_TARGET_ROOTn(IMX8M_ARM_A53_CLK_ROOT),
+ CCM_TARGET_ROOT0_DIV,
+ FIELD_PREP(CCM_TARGET_ROOT0_DIV, 0));
+}
+
+#define KEEP_ALIVE 0x18
+#define VER_L 0x1c
+#define VER_H 0x20
+#define VER_LIB_L_ADDR 0x24
+#define VER_LIB_H_ADDR 0x28
+#define FW_ALIVE_TIMEOUT_US 100000
+
+static int imx8mq_report_hdmi_firmware(void)
+{
+ void __iomem *hdmi = IOMEM(MX8MQ_HDMI_CTRL_BASE_ADDR);
+ u16 ver_lib, ver;
+ u32 reg;
+ int ret;
+
+ if (!cpu_is_mx8mq())
+ return 0;
+
+ /* check the keep alive register to make sure fw working */
+ ret = readl_poll_timeout(hdmi + KEEP_ALIVE,
+ reg, reg, FW_ALIVE_TIMEOUT_US);
+ if (ret < 0) {
+ pr_info("HDP firmware is not running\n");
+ return 0;
+ }
+
+ ver = readl(hdmi + VER_H) & 0xff;
+ ver <<= 8;
+ ver |= readl(hdmi + VER_L) & 0xff;
+
+ ver_lib = readl(hdmi + VER_LIB_H_ADDR) & 0xff;
+ ver_lib <<= 8;
+ ver_lib |= readl(hdmi + VER_LIB_L_ADDR) & 0xff;
+
+ pr_info("HDP firmware ver: %d ver_lib: %d\n", ver, ver_lib);
+
+ return 0;
+}
+console_initcall(imx8mq_report_hdmi_firmware);
+
+void imx8m_early_setup_uart_clock(void)
+{
+ imx8m_ccgr_clock_disable(IMX8M_CCM_CCGR_UART1);
+ imx8m_ccgr_clock_disable(IMX8M_CCM_CCGR_UART2);
+ imx8m_ccgr_clock_disable(IMX8M_CCM_CCGR_UART3);
+ imx8m_ccgr_clock_disable(IMX8M_CCM_CCGR_UART4);
+
+ imx8m_clock_set_target_val(IMX8M_UART1_CLK_ROOT,
+ IMX8M_CCM_TARGET_ROOTn_ENABLE |
+ IMX8M_UART1_CLK_ROOT__25M_REF_CLK);
+ imx8m_clock_set_target_val(IMX8M_UART2_CLK_ROOT,
+ IMX8M_CCM_TARGET_ROOTn_ENABLE |
+ IMX8M_UART1_CLK_ROOT__25M_REF_CLK);
+ imx8m_clock_set_target_val(IMX8M_UART3_CLK_ROOT,
+ IMX8M_CCM_TARGET_ROOTn_ENABLE |
+ IMX8M_UART1_CLK_ROOT__25M_REF_CLK);
+ imx8m_clock_set_target_val(IMX8M_UART4_CLK_ROOT,
+ IMX8M_CCM_TARGET_ROOTn_ENABLE |
+ IMX8M_UART1_CLK_ROOT__25M_REF_CLK);
+
+ imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_UART1);
+ imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_UART2);
+ imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_UART3);
+ imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_UART4);
+}
diff --git a/arch/arm/mach-imx/imx8mq.c b/arch/arm/mach-imx/imx8mq.c
deleted file mode 100644
index d06ba09..0000000
--- a/arch/arm/mach-imx/imx8mq.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <init.h>
-#include <common.h>
-#include <io.h>
-#include <asm/syscounter.h>
-#include <asm/system.h>
-#include <mach/generic.h>
-#include <mach/revision.h>
-#include <mach/imx8mq.h>
-#include <mach/reset-reason.h>
-#include <mach/ocotp.h>
-
-#include <linux/iopoll.h>
-#include <linux/arm-smccc.h>
-
-#define FSL_SIP_BUILDINFO 0xC2000003
-#define FSL_SIP_BUILDINFO_GET_COMMITHASH 0x00
-
-u64 imx8mq_uid(void)
-{
- return imx_ocotp_read_uid(IOMEM(MX8MQ_OCOTP_BASE_ADDR));
-}
-
-int imx8mq_init(void)
-{
- void __iomem *anatop = IOMEM(MX8MQ_ANATOP_BASE_ADDR);
- void __iomem *src = IOMEM(MX8MQ_SRC_BASE_ADDR);
- uint32_t type = FIELD_GET(DIGPROG_MAJOR,
- readl(anatop + MX8MQ_ANATOP_DIGPROG));
- struct arm_smccc_res res;
- const char *cputypestr;
-
- imx8_boot_save_loc();
-
- switch (type) {
- case IMX8M_CPUTYPE_IMX8MQ:
- cputypestr = "i.MX8MQ";
- break;
- default:
- cputypestr = "unknown i.MX8M";
- break;
- };
-
- imx_set_silicon_revision(cputypestr, imx8mq_cpu_revision());
- /*
- * Reset reasons seem to be identical to that of i.MX7
- */
- imx_set_reset_reason(src + IMX7_SRC_SRSR, imx7_reset_reasons);
- pr_info("%s unique ID: %llx\n", cputypestr, imx8mq_uid());
-
- if (IS_ENABLED(CONFIG_ARM_SMCCC) &&
- IS_ENABLED(CONFIG_FIRMWARE_IMX8MQ_ATF)) {
- arm_smccc_smc(FSL_SIP_BUILDINFO,
- FSL_SIP_BUILDINFO_GET_COMMITHASH,
- 0, 0, 0, 0, 0, 0, &res);
- pr_info("i.MX ARM Trusted Firmware: %s\n", (char *)&res.a0);
- }
-
- return 0;
-}
-
-#define KEEP_ALIVE 0x18
-#define VER_L 0x1c
-#define VER_H 0x20
-#define VER_LIB_L_ADDR 0x24
-#define VER_LIB_H_ADDR 0x28
-#define FW_ALIVE_TIMEOUT_US 100000
-
-static int imx8mq_report_hdmi_firmware(void)
-{
- void __iomem *hdmi = IOMEM(MX8MQ_HDMI_CTRL_BASE_ADDR);
- u16 ver_lib, ver;
- u32 reg;
- int ret;
-
- if (!cpu_is_mx8mq())
- return 0;
-
- /* check the keep alive register to make sure fw working */
- ret = readl_poll_timeout(hdmi + KEEP_ALIVE,
- reg, reg, FW_ALIVE_TIMEOUT_US);
- if (ret < 0) {
- pr_info("HDP firmware is not running\n");
- return 0;
- }
-
- ver = readl(hdmi + VER_H) & 0xff;
- ver <<= 8;
- ver |= readl(hdmi + VER_L) & 0xff;
-
- ver_lib = readl(hdmi + VER_LIB_H_ADDR) & 0xff;
- ver_lib <<= 8;
- ver_lib |= readl(hdmi + VER_LIB_L_ADDR) & 0xff;
-
- pr_info("HDP firmware ver: %d ver_lib: %d\n", ver, ver_lib);
-
- return 0;
-}
-console_initcall(imx8mq_report_hdmi_firmware);
diff --git a/arch/arm/mach-imx/include/mach/atf.h b/arch/arm/mach-imx/include/mach/atf.h
index aeb24ba..f64a9dd 100644
--- a/arch/arm/mach-imx/include/mach/atf.h
+++ b/arch/arm/mach-imx/include/mach/atf.h
@@ -4,10 +4,15 @@
#include <linux/sizes.h>
#include <asm/system.h>
-#define MX8MQ_ATF_BL31_SIZE_LIMIT SZ_64K
+#define MX8M_ATF_BL31_SIZE_LIMIT SZ_64K
+
+#define MX8MM_ATF_BL31_BASE_ADDR 0x00920000
#define MX8MQ_ATF_BL31_BASE_ADDR 0x00910000
-#define MX8MQ_ATF_BL33_BASE_ADDR 0x40200000
+#define MX8M_ATF_BL33_BASE_ADDR 0x40200000
+#define MX8MM_ATF_BL33_BASE_ADDR MX8M_ATF_BL33_BASE_ADDR
+#define MX8MQ_ATF_BL33_BASE_ADDR MX8M_ATF_BL33_BASE_ADDR
+void imx8mm_atf_load_bl31(const void *fw, size_t fw_size);
void imx8mq_atf_load_bl31(const void *fw, size_t fw_size);
#endif \ No newline at end of file
diff --git a/arch/arm/mach-imx/include/mach/debug_ll.h b/arch/arm/mach-imx/include/mach/debug_ll.h
index 1550e05..5eed016 100644
--- a/arch/arm/mach-imx/include/mach/debug_ll.h
+++ b/arch/arm/mach-imx/include/mach/debug_ll.h
@@ -98,7 +98,7 @@ static inline void vf610_uart_setup_ll(void)
lpuart_setup(base, 66000000);
}
-static inline void imx8_uart_setup_ll(void)
+static inline void imx8m_uart_setup_ll(void)
{
void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC,
CONFIG_DEBUG_IMX_UART_PORT));
@@ -127,7 +127,7 @@ static inline void imx53_uart_setup_ll(void) {}
static inline void imx6_uart_setup_ll(void) {}
static inline void imx7_uart_setup_ll(void) {}
static inline void vf610_uart_setup_ll(void) {}
-static inline void imx8_uart_setup_ll(void) {}
+static inline void imx8m_uart_setup_ll(void) {}
#endif /* CONFIG_DEBUG_LL */
diff --git a/arch/arm/mach-imx/include/mach/esdctl.h b/arch/arm/mach-imx/include/mach/esdctl.h
index 18c4a28..41eb9f6 100644
--- a/arch/arm/mach-imx/include/mach/esdctl.h
+++ b/arch/arm/mach-imx/include/mach/esdctl.h
@@ -139,6 +139,7 @@ void __noreturn imx53_barebox_entry(void *boarddata);
void __noreturn imx6q_barebox_entry(void *boarddata);
void __noreturn imx6ul_barebox_entry(void *boarddata);
void __noreturn vf610_barebox_entry(void *boarddata);
+void __noreturn imx8mm_barebox_entry(void *boarddata);
void __noreturn imx8mq_barebox_entry(void *boarddata);
void __noreturn imx7d_barebox_entry(void *boarddata);
#define imx6sx_barebox_entry(boarddata) imx6ul_barebox_entry(boarddata)
diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h
index 5102c34..7742a00 100644
--- a/arch/arm/mach-imx/include/mach/generic.h
+++ b/arch/arm/mach-imx/include/mach/generic.h
@@ -16,7 +16,8 @@ void imx53_boot_save_loc(void);
void imx6_boot_save_loc(void);
void imx7_boot_save_loc(void);
void vf610_boot_save_loc(void);
-void imx8_boot_save_loc(void);
+void imx8mm_boot_save_loc(void);
+void imx8mq_boot_save_loc(void);
void imx25_get_boot_source(enum bootsource *src, int *instance);
void imx27_get_boot_source(enum bootsource *src, int *instance);
@@ -26,7 +27,8 @@ void imx53_get_boot_source(enum bootsource *src, int *instance);
void imx6_get_boot_source(enum bootsource *src, int *instance);
void imx7_get_boot_source(enum bootsource *src, int *instance);
void vf610_get_boot_source(enum bootsource *src, int *instance);
-void imx8_get_boot_source(enum bootsource *src, int *instance);
+void imx8mm_get_boot_source(enum bootsource *src, int *instance);
+void imx8mq_get_boot_source(enum bootsource *src, int *instance);
int imx1_init(void);
int imx21_init(void);
@@ -40,6 +42,7 @@ int imx53_init(void);
int imx6_init(void);
int imx7_init(void);
int vf610_init(void);
+int imx8mm_init(void);
int imx8mq_init(void);
int imx1_devices_init(void);
@@ -59,6 +62,7 @@ void imx6ul_cpu_lowlevel_init(void);
void imx7_cpu_lowlevel_init(void);
void vf610_cpu_lowlevel_init(void);
void imx8mq_cpu_lowlevel_init(void);
+void imx8mm_cpu_lowlevel_init(void);
/* There's a off-by-one betweem the gpio bank number and the gpiochip */
/* range e.g. GPIO_1_5 is gpio 5 under linux */
@@ -199,6 +203,18 @@ extern unsigned int __imx_cpu_type;
# define cpu_is_mx7() (0)
#endif
+#ifdef CONFIG_ARCH_IMX8MM
+# ifdef imx_cpu_type
+# undef imx_cpu_type
+# define imx_cpu_type __imx_cpu_type
+# else
+# define imx_cpu_type IMX_CPU_IMX8MM
+# endif
+# define cpu_is_mx8mm() (imx_cpu_type == IMX_CPU_IMX8MM)
+#else
+# define cpu_is_mx8mm() (0)
+#endif
+
#ifdef CONFIG_ARCH_IMX8MQ
# ifdef imx_cpu_type
# undef imx_cpu_type
@@ -235,4 +251,6 @@ extern unsigned int __imx_cpu_type;
#define cpu_is_mx23() (0)
#define cpu_is_mx28() (0)
+#define cpu_is_mx8m() (cpu_is_mx8mq() || cpu_is_mx8mm())
+
#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-imx/include/mach/imx7-ccm-regs.h b/arch/arm/mach-imx/include/mach/imx7-ccm-regs.h
index 43b9425..de6eb1b 100644
--- a/arch/arm/mach-imx/include/mach/imx7-ccm-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx7-ccm-regs.h
@@ -1,21 +1,48 @@
#ifndef __MACH_IMX7_CCM_REGS_H__
#define __MACH_IMX7_CCM_REGS_H__
-#include "ccm.h"
+#define IMX7_CCM_CCGR_UART1 148
+#define IMX7_CCM_CCGR_UART2 149
-#define CCM_CCGR_UART1 148
-#define CCM_CCGR_UART2 149
-
-#define CLOCK_ROOT_INDEX(x) (((x) - 0x8000) / 128)
+#define IMX7_CLOCK_ROOT_INDEX(x) (((x) - 0x8000) / 128)
/*
* Taken from "Table 5-11. Clock Root Table" from i.MX7 Dual Processor
* Reference Manual
*/
-#define UART1_CLK_ROOT CLOCK_ROOT_INDEX(0xaf80)
-#define UART1_CLK_ROOT__OSC_24M CCM_TARGET_ROOTn_MUX(0b000)
+#define IMX7_UART1_CLK_ROOT IMX7_CLOCK_ROOT_INDEX(0xaf80)
+#define IMX7_UART1_CLK_ROOT__OSC_24M IMX7_CCM_TARGET_ROOTn_MUX(0b000)
+
+#define IMX7_UART2_CLK_ROOT IMX7_CLOCK_ROOT_INDEX(0xb000)
+#define IMX7_UART2_CLK_ROOT__OSC_24M IMX7_CCM_TARGET_ROOTn_MUX(0b000)
+
+/* 0 <= n <= 190 */
+#define IMX7_CCM_CCGRn_SET(n) (0x4004 + 16 * (n))
+#define IMX7_CCM_CCGRn_CLR(n) (0x4008 + 16 * (n))
+
+/* 0 <= n <= 120 */
+#define IMX7_CCM_TARGET_ROOTn(n) (0x8000 + 128 * (n))
+
+#define IMX7_CCM_TARGET_ROOTn_MUX(x) ((x) << 24)
+#define IMX7_CCM_TARGET_ROOTn_ENABLE BIT(28)
+
+
+#define IMX7_CCM_CCGR_SETTINGn(n, s) ((s) << ((n) * 4))
+#define IMX7_CCM_CCGR_SETTINGn_NOT_NEEDED(n) IMX7_CCM_CCGR_SETTINGn(n, 0b00)
+#define IMX7_CCM_CCGR_SETTINGn_NEEDED_RUN(n) IMX7_CCM_CCGR_SETTINGn(n, 0b01)
+#define IMX7_CCM_CCGR_SETTINGn_NEEDED_RUN_WAIT(n) IMX7_CCM_CCGR_SETTINGn(n, 0b10)
+#define IMX7_CCM_CCGR_SETTINGn_NEEDED(n) IMX7_CCM_CCGR_SETTINGn(n, 0b11)
+
+static inline void imx7_early_setup_uart_clock(void)
+{
+ void __iomem *ccm = IOMEM(MX7_CCM_BASE_ADDR);
-#define UART2_CLK_ROOT CLOCK_ROOT_INDEX(0xb000)
-#define UART2_CLK_ROOT__OSC_24M CCM_TARGET_ROOTn_MUX(0b000)
+ writel(IMX7_CCM_CCGR_SETTINGn_NEEDED(0),
+ ccm + IMX7_CCM_CCGRn_CLR(IMX7_CCM_CCGR_UART1));
+ writel(IMX7_CCM_TARGET_ROOTn_ENABLE | IMX7_UART1_CLK_ROOT__OSC_24M,
+ ccm + IMX7_CCM_TARGET_ROOTn(IMX7_UART1_CLK_ROOT));
+ writel(IMX7_CCM_CCGR_SETTINGn_NEEDED(0),
+ ccm + IMX7_CCM_CCGRn_SET(IMX7_CCM_CCGR_UART1));
+}
#endif
diff --git a/arch/arm/mach-imx/include/mach/imx8-ccm-regs.h b/arch/arm/mach-imx/include/mach/imx8-ccm-regs.h
deleted file mode 100644
index 93b584e..0000000
--- a/arch/arm/mach-imx/include/mach/imx8-ccm-regs.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef __MACH_IMX8_CCM_REGS_H__
-#define __MACH_IMX8_CCM_REGS_H__
-
-#include "ccm.h"
-
-#define CCM_CCGR_UART1 73
-
-/*
- * Taken from "Table 5-1. Clock Root Table" from i.MX8M Quad
- * Applications Processor Reference Manual
- */
-#define UART1_CLK_ROOT 94
-#define UART1_CLK_ROOT__25M_REF_CLK CCM_TARGET_ROOTn_MUX(0b000)
-
-#endif
diff --git a/arch/arm/mach-imx/include/mach/imx8-ddrc.h b/arch/arm/mach-imx/include/mach/imx8-ddrc.h
deleted file mode 100644
index d49e29f..0000000
--- a/arch/arm/mach-imx/include/mach/imx8-ddrc.h
+++ /dev/null
@@ -1,66 +0,0 @@
-#ifndef __IMX8_DDRC_H__
-#define __IMX8_DDRC_H__
-
-#include <mach/imx8mq-regs.h>
-#include <io.h>
-#include <firmware.h>
-#include <linux/compiler.h>
-
-enum ddrc_phy_firmware_offset {
- DDRC_PHY_IMEM = 0x00050000U,
- DDRC_PHY_DMEM = 0x00054000U,
-};
-
-void ddrc_phy_load_firmware(void __iomem *,
- enum ddrc_phy_firmware_offset,
- const u16 *, size_t);
-
-#define DDRC_PHY_REG(x) ((x) * 4)
-
-void ddrc_phy_wait_training_complete(void __iomem *phy);
-
-
-/*
- * i.MX8M DDR Tool compatibility layer
- */
-
-#define reg32_write(a, v) writel(v, a)
-#define reg32_read(a) readl(a)
-
-static inline void wait_ddrphy_training_complete(void)
-{
- ddrc_phy_wait_training_complete(IOMEM(MX8MQ_DDRC_PHY_BASE_ADDR));
-}
-
-#define __ddr_load_train_code(imem, dmem) \
- do { \
- const u16 *__mem; \
- size_t __size; \
- \
- get_builtin_firmware(imem, &__mem, &__size); \
- ddrc_phy_load_firmware(IOMEM(MX8MQ_DDRC_PHY_BASE_ADDR), \
- DDRC_PHY_IMEM, __mem, __size); \
- \
- get_builtin_firmware(dmem, &__mem, &__size); \
- ddrc_phy_load_firmware(IOMEM(MX8MQ_DDRC_PHY_BASE_ADDR), \
- DDRC_PHY_DMEM, __mem, __size); \
- } while (0)
-
-#define ddr_load_train_code(imem_dmem) __ddr_load_train_code(imem_dmem)
-
-#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + (X * 0x2000000))
-
-#define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04)
-#define DDRC_MRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18)
-#define DDRC_PWRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x30)
-#define DDRC_RFSHCTL3(X) (DDRC_IPS_BASE_ADDR(X) + 0x60)
-#define DDRC_CRCPARSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xcc)
-#define DDRC_DFIMISC(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b0)
-#define DDRC_DFISTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1bc)
-#define DDRC_SWCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x320)
-#define DDRC_SWSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x324)
-#define DDRC_PCTRL_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x490)
-
-#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000))
-
-#endif \ No newline at end of file
diff --git a/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h b/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h
new file mode 100644
index 0000000..743ed6c
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h
@@ -0,0 +1,57 @@
+#ifndef __MACH_IMX8_CCM_REGS_H__
+#define __MACH_IMX8_CCM_REGS_H__
+
+#include <mach/imx8mq-regs.h>
+
+#define IMX8M_CCM_CCGR_DDR1 5
+#define IMX8M_CCM_CCGR_I2C1 23
+#define IMX8M_CCM_CCGR_I2C2 24
+#define IMX8M_CCM_CCGR_I2C3 25
+#define IMX8M_CCM_CCGR_I2C4 26
+#define IMX8M_CCM_CCGR_SCTR 57
+#define IMX8M_CCM_CCGR_UART1 73
+#define IMX8M_CCM_CCGR_UART2 74
+#define IMX8M_CCM_CCGR_UART3 75
+#define IMX8M_CCM_CCGR_UART4 76
+#define IMX8M_CCM_CCGR_GIC 92
+
+/*
+ * Taken from "Table 5-1. Clock Root Table" from i.MX8M Quad
+ * Applications Processor Reference Manual
+ */
+#define IMX8M_ARM_A53_CLK_ROOT 0
+#define IMX8M_DRAM_SEL_CFG 48
+#define IMX8M_DRAM_ALT_CLK_ROOT 64
+#define IMX8M_DRAM_APB_CLK_ROOT 65
+#define IMX8M_UART1_CLK_ROOT 94
+#define IMX8M_UART2_CLK_ROOT 95
+#define IMX8M_UART3_CLK_ROOT 96
+#define IMX8M_UART4_CLK_ROOT 97
+#define IMX8M_GIC_CLK_ROOT 100
+#define IMX8M_UART1_CLK_ROOT__25M_REF_CLK IMX8M_CCM_TARGET_ROOTn_MUX(0b000)
+
+/* 0 <= n <= 190 */
+#define IMX8M_CCM_CCGRn_SET(n) (0x4004 + 16 * (n))
+#define IMX8M_CCM_CCGRn_CLR(n) (0x4008 + 16 * (n))
+
+/* 0 <= n <= 120 */
+#define IMX8M_CCM_TARGET_ROOTn(n) (0x8000 + 128 * (n))
+
+#define IMX8M_CCM_TARGET_ROOTn_POST_DIV(n) ((n) & 0x0000003f)
+#define IMX8M_CCM_TARGET_ROOTn_PRE_DIV(n) (((n) << 16) & 0x00070000)
+#define IMX8M_CCM_TARGET_ROOTn_MUX(x) ((x) << 24)
+#define IMX8M_CCM_TARGET_ROOTn_ENABLE BIT(28)
+
+#define IMX8M_CCM_CCGR_SETTINGn(n, s) ((s) << ((n) * 4))
+#define IMX8M_CCM_CCGR_SETTINGn_NOT_NEEDED(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b00)
+#define IMX8M_CCM_CCGR_SETTINGn_NEEDED_RUN(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b01)
+#define IMX8M_CCM_CCGR_SETTINGn_NEEDED_RUN_WAIT(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b10)
+#define IMX8M_CCM_CCGR_SETTINGn_NEEDED(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b11)
+
+void imx8m_early_setup_uart_clock(void);
+void imx8mm_early_clock_init(void);
+void imx8m_clock_set_target_val(int clock_id, u32 val);
+void imx8m_ccgr_clock_enable(int index);
+void imx8m_ccgr_clock_disable(int index);
+
+#endif
diff --git a/arch/arm/mach-imx/include/mach/imx8m-regs.h b/arch/arm/mach-imx/include/mach/imx8m-regs.h
new file mode 100644
index 0000000..e5f466c
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/imx8m-regs.h
@@ -0,0 +1,37 @@
+#ifndef __MACH_IMX8M_REGS_H
+#define __MACH_IMX8M_REGS_H
+
+#define MX8M_GPIO1_BASE_ADDR 0X30200000
+#define MX8M_GPIO2_BASE_ADDR 0x30210000
+#define MX8M_GPIO3_BASE_ADDR 0x30220000
+#define MX8M_GPIO4_BASE_ADDR 0x30230000
+#define MX8M_GPIO5_BASE_ADDR 0x30240000
+#define MX8M_WDOG1_BASE_ADDR 0x30280000
+#define MX8M_WDOG2_BASE_ADDR 0x30290000
+#define MX8M_WDOG3_BASE_ADDR 0x302A0000
+#define MX8M_IOMUXC_BASE_ADDR 0x30330000
+#define MX8M_IOMUXC_GPR_BASE_ADDR 0x30340000
+#define MX8M_OCOTP_BASE_ADDR 0x30350000
+#define MX8M_ANATOP_BASE_ADDR 0x30360000
+#define MX8M_CCM_BASE_ADDR 0x30380000
+#define MX8M_SRC_BASE_ADDR 0x30390000
+#define MX8M_SRC_DDRC_RCR_ADDR 0x30391000
+#define MX8M_GPC_BASE_ADDR 0x303A0000
+#define MX8M_SYSCNT_CTRL_BASE_ADDR 0x306C0000
+#define MX8M_UART1_BASE_ADDR 0x30860000
+#define MX8M_UART3_BASE_ADDR 0x30880000
+#define MX8M_UART2_BASE_ADDR 0x30890000
+#define MX8M_I2C1_BASE_ADDR 0x30A20000
+#define MX8M_I2C2_BASE_ADDR 0x30A30000
+#define MX8M_I2C3_BASE_ADDR 0x30A40000
+#define MX8M_I2C4_BASE_ADDR 0x30A50000
+#define MX8M_UART4_BASE_ADDR 0x30A60000
+#define MX8M_USDHC1_BASE_ADDR 0x30B40000
+#define MX8M_USDHC2_BASE_ADDR 0x30B50000
+#define MX8M_DDRC_PHY_BASE_ADDR 0x3c000000
+#define MX8M_DDRC_DDR_SS_GPR0 (MX8M_DDRC_PHY_BASE_ADDR + 0x01000000)
+#define MX8M_DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000))
+#define MX8M_DDRC_CTL_BASE_ADDR MX8M_DDRC_IPS_BASE_ADDR(0)
+#define MX8M_DDR_CSD1_BASE_ADDR 0x40000000
+
+#endif /* __MACH_IMX8M_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/imx8mm-regs.h b/arch/arm/mach-imx/include/mach/imx8mm-regs.h
new file mode 100644
index 0000000..1325c78
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/imx8mm-regs.h
@@ -0,0 +1,46 @@
+#ifndef __MACH_IMX8MM_REGS_H
+#define __MACH_IMX8MM_REGS_H
+
+#include <mach/imx8m-regs.h>
+
+#define MX8MM_M4_BOOTROM_BASE_ADDR 0x007e0000
+
+#define MX8MM_GPIO1_BASE_ADDR 0x30200000
+#define MX8MM_GPIO2_BASE_ADDR 0x30210000
+#define MX8MM_GPIO3_BASE_ADDR 0x30220000
+#define MX8MM_GPIO4_BASE_ADDR 0x30230000
+#define MX8MM_GPIO5_BASE_ADDR 0x30240000
+#define MX8MM_WDOG1_BASE_ADDR 0x30280000
+#define MX8MM_WDOG2_BASE_ADDR 0x30290000
+#define MX8MM_WDOG3_BASE_ADDR 0x302a0000
+#define MX8MM_IOMUXC_BASE_ADDR 0x30330000
+#define MX8MM_IOMUXC_GPR_BASE_ADDR 0x30340000
+#define MX8MM_OCOTP_BASE_ADDR 0x30350000
+#define MX8MM_ANATOP_BASE_ADDR 0x30360000
+#define MX8MM_CCM_BASE_ADDR 0x30380000
+#define MX8MM_SRC_BASE_ADDR 0x30390000
+#define MX8MM_GPC_BASE_ADDR 0x303a0000
+#define MX8MM_SYSCNT_RD_BASE_ADDR 0x306a0000
+#define MX8MM_SYSCNT_CMP_BASE_ADDR 0x306b0000
+#define MX8MM_SYSCNT_CTRL_BASE_ADDR 0x306c0000
+#define MX8MM_UART1_BASE_ADDR 0x30860000
+#define MX8MM_UART3_BASE_ADDR 0x30880000
+#define MX8MM_UART2_BASE_ADDR 0x30890000
+#define MX8MM_I2C1_BASE_ADDR 0x30a20000
+#define MX8MM_I2C2_BASE_ADDR 0x30a30000
+#define MX8MM_I2C3_BASE_ADDR 0x30a40000
+#define MX8MM_I2C4_BASE_ADDR 0x30a50000
+#define MX8MM_UART4_BASE_ADDR 0x30a60000
+#define MX8MM_USDHC1_BASE_ADDR 0x30b40000
+#define MX8MM_USDHC2_BASE_ADDR 0x30b50000
+#define MX8MM_USDHC3_BASE_ADDR 0x30b60000
+#define MX8MM_USB1_BASE_ADDR 0x32e40000
+#define MX8MM_USB2_BASE_ADDR 0x32e50000
+#define MX8MM_TZASC_BASE_ADDR 0x32f80000
+#define MX8MM_SRC_IPS_BASE_ADDR 0x30390000
+#define MX8MM_SRC_DDRC_RCR_ADDR 0x30391000
+#define MX8MM_SRC_DDRC2_RCR_ADDR 0x30391004
+#define MX8MM_DDRC_DDR_SS_GPR0 0x3d000000
+#define MX8MM_DDR_CSD1_BASE_ADDR 0x40000000
+
+#endif /* __MACH_IMX8MM_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/imx8mq-regs.h b/arch/arm/mach-imx/include/mach/imx8mq-regs.h
index 51936f5..2f6488a 100644
--- a/arch/arm/mach-imx/include/mach/imx8mq-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx8mq-regs.h
@@ -1,6 +1,8 @@
#ifndef __MACH_IMX8MQ_REGS_H
#define __MACH_IMX8MQ_REGS_H
+#include <mach/imx8m-regs.h>
+
#define MX8MQ_M4_BOOTROM_BASE_ADDR 0x007E0000
#define MX8MQ_SAI1_BASE_ADDR 0x30010000
diff --git a/arch/arm/mach-imx/include/mach/imx8mq.h b/arch/arm/mach-imx/include/mach/imx8mq.h
index c085894..2ef2987 100644
--- a/arch/arm/mach-imx/include/mach/imx8mq.h
+++ b/arch/arm/mach-imx/include/mach/imx8mq.h
@@ -4,6 +4,7 @@
#include <io.h>
#include <mach/generic.h>
#include <mach/imx8mq-regs.h>
+#include <mach/imx8mm-regs.h>
#include <mach/revision.h>
#include <linux/bitfield.h>
@@ -13,11 +14,21 @@
#define IMX8MQ_OCOTP_VERSION_B1_MAGIC 0xff0055aa
#define MX8MQ_ANATOP_DIGPROG 0x6c
+#define MX8MM_ANATOP_DIGPROG 0x800
#define DIGPROG_MAJOR GENMASK(23, 8)
#define DIGPROG_MINOR GENMASK(7, 0)
#define IMX8M_CPUTYPE_IMX8MQ 0x8240
+#define IMX8M_CPUTYPE_IMX8MM 0x8241
+
+static inline int imx8mm_cpu_revision(void)
+{
+ void __iomem *anatop = IOMEM(MX8MM_ANATOP_BASE_ADDR);
+ uint32_t revision = FIELD_GET(DIGPROG_MINOR,
+ readl(anatop + MX8MM_ANATOP_DIGPROG));
+ return revision;
+}
static inline int imx8mq_cpu_revision(void)
{
@@ -49,6 +60,6 @@ static inline int imx8mq_cpu_revision(void)
return revision;
}
-u64 imx8mq_uid(void);
+u64 imx8m_uid(void);
#endif /* __MACH_IMX8_H */ \ No newline at end of file
diff --git a/arch/arm/mach-imx/include/mach/imx_cpu_types.h b/arch/arm/mach-imx/include/mach/imx_cpu_types.h
index 754fb98..b3fccfa 100644
--- a/arch/arm/mach-imx/include/mach/imx_cpu_types.h
+++ b/arch/arm/mach-imx/include/mach/imx_cpu_types.h
@@ -13,6 +13,7 @@
#define IMX_CPU_IMX6 6
#define IMX_CPU_IMX7 7
#define IMX_CPU_IMX8MQ 8
+#define IMX_CPU_IMX8MM 81
#define IMX_CPU_VF610 610
#endif /* __MACH_IMX_CPU_TYPES_H */
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx7.h b/arch/arm/mach-imx/include/mach/iomux-mx7.h
index 2667dc3..def9cf4 100644
--- a/arch/arm/mach-imx/include/mach/iomux-mx7.h
+++ b/arch/arm/mach-imx/include/mach/iomux-mx7.h
@@ -8,6 +8,7 @@
#define __MACH_IOMUX_IMX7D_H__
#include <mach/iomux-v3.h>
+#include <mach/imx7-regs.h>
enum {
MX7D_PAD_GPIO1_IO00__GPIO1_IO0 = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0),
@@ -1306,8 +1307,9 @@ enum {
MX7D_PAD_ENET1_COL__CSU_INT_DEB = IOMUX_PAD(0x04D8, 0x0268, 7, 0x0000, 0, 0),
};
-static inline void mx7_setup_pad(void __iomem *iomux, iomux_v3_cfg_t pad)
+static inline void imx7_setup_pad(iomux_v3_cfg_t pad)
{
+ void __iomem *iomux = IOMEM(MX7_IOMUXC_BASE_ADDR);
unsigned int flags = 0;
uint32_t mode = IOMUX_MODE(pad);
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx8m.h b/arch/arm/mach-imx/include/mach/iomux-mx8m.h
new file mode 100644
index 0000000..de66750
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/iomux-mx8m.h
@@ -0,0 +1,27 @@
+#ifndef __MACH_IOMUX_IMX8M_H__
+#define __MACH_IOMUX_IMX8M_H__
+
+#include <mach/iomux-v3.h>
+
+#define PAD_CTL_DSE_3P3V_45_OHM 0b110
+
+static inline void imx8m_setup_pad(void __iomem *iomux, iomux_v3_cfg_t pad)
+{
+ unsigned int flags = 0;
+ uint32_t mode = IOMUX_MODE(pad);
+
+ if (mode & IOMUX_CONFIG_LPSR) {
+ mode &= ~IOMUX_CONFIG_LPSR;
+ flags = ZERO_OFFSET_VALID | IMX7_PINMUX_LPSR;
+ }
+
+ iomux_v3_setup_pad(iomux, flags,
+ IOMUX_CTRL_OFS(pad),
+ IOMUX_PAD_CTRL_OFS(pad),
+ IOMUX_SEL_INPUT_OFS(pad),
+ mode,
+ IOMUX_PAD_CTRL(pad),
+ IOMUX_SEL_INPUT(pad));
+}
+
+#endif /* __MACH_IOMUX_IMX8MQ_H__ */
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx8mm.h b/arch/arm/mach-imx/include/mach/iomux-mx8mm.h
new file mode 100644
index 0000000..f916718
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/iomux-mx8mm.h
@@ -0,0 +1,701 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8MM_PINS_H__
+#define __ASM_ARCH_IMX8MM_PINS_H__
+
+#include <mach/iomux-v3.h>
+#include <mach/imx8mm-regs.h>
+#include <mach/iomux-mx8m.h>
+
+enum {
+ IMX8MM_PAD_GPIO1_IO00_GPIO1_IO0 = IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT = IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO00_XTALOSC_REF_CLK_32K = IOMUX_PAD(0x0290, 0x0028, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO00_CCM_EXT_CLK1 = IOMUX_PAD(0x0290, 0x0028, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO01_GPIO1_IO1 = IOMUX_PAD(0x0294, 0x002C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO01_PWM1_OUT = IOMUX_PAD(0x0294, 0x002C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO01_XTALOSC_REF_CLK_24M = IOMUX_PAD(0x0294, 0x002C, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO01_CCM_EXT_CLK2 = IOMUX_PAD(0x0294, 0x002C, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO02_GPIO1_IO2 = IOMUX_PAD(0x0298, 0x0030, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B = IOMUX_PAD(0x0298, 0x0030, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_ANY = IOMUX_PAD(0x0298, 0x0030, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO03_GPIO1_IO3 = IOMUX_PAD(0x029C, 0x0034, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO03_USDHC1_VSELECT = IOMUX_PAD(0x029C, 0x0034, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO03_SDMA1_EXT_EVENT0 = IOMUX_PAD(0x029C, 0x0034, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO04_GPIO1_IO4 = IOMUX_PAD(0x02A0, 0x0038, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO04_USDHC2_VSELECT = IOMUX_PAD(0x02A0, 0x0038, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO04_SDMA1_EXT_EVENT1 = IOMUX_PAD(0x02A0, 0x0038, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO05_GPIO1_IO5 = IOMUX_PAD(0x02A4, 0x003C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO05_ARM_PLATFORM_M4_NMI = IOMUX_PAD(0x02A4, 0x003C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO05_CCM_PMIC_READY = IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0),
+ IMX8MM_PAD_GPIO1_IO05_SRC_INT_BOOT = IOMUX_PAD(0x02A4, 0x003C, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO06_GPIO1_IO6 = IOMUX_PAD(0x02A8, 0x0040, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO06_ENET1_MDC = IOMUX_PAD(0x02A8, 0x0040, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO06_USDHC1_CD_B = IOMUX_PAD(0x02A8, 0x0040, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO06_CCM_EXT_CLK3 = IOMUX_PAD(0x02A8, 0x0040, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO07_GPIO1_IO7 = IOMUX_PAD(0x02AC, 0x0044, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO07_ENET1_MDIO = IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0),
+ IMX8MM_PAD_GPIO1_IO07_USDHC1_WP = IOMUX_PAD(0x02AC, 0x0044, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO07_CCM_EXT_CLK4 = IOMUX_PAD(0x02AC, 0x0044, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO08_GPIO1_IO8 = IOMUX_PAD(0x02B0, 0x0048, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO08_ENET1_1588_EVENT0_IN = IOMUX_PAD(0x02B0, 0x0048, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO08_USDHC2_RESET_B = IOMUX_PAD(0x02B0, 0x0048, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO08_CCM_WAIT = IOMUX_PAD(0x02B0, 0x0048, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO09_GPIO1_IO9 = IOMUX_PAD(0x02B4, 0x004C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO09_ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x02B4, 0x004C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO09_USDHC3_RESET_B = IOMUX_PAD(0x02B4, 0x004C, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO09_SDMA2_EXT_EVENT0 = IOMUX_PAD(0x02B4, 0x004C, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO09_CCM_STOP = IOMUX_PAD(0x02B4, 0x004C, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO10_GPIO1_IO10 = IOMUX_PAD(0x02B8, 0x0050, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO10_USB1_OTG_ID = IOMUX_PAD(0x02B8, 0x0050, 1, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO11_GPIO1_IO11 = IOMUX_PAD(0x02BC, 0x0054, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO11_USB2_OTG_ID = IOMUX_PAD(0x02BC, 0x0054, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO11_USDHC3_VSELECT = IOMUX_PAD(0x02BC, 0x0054, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO11_CCM_PMIC_READY = IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0),
+ IMX8MM_PAD_GPIO1_IO11_CCM_OUT0 = IOMUX_PAD(0x02BC, 0x0054, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO12_GPIO1_IO12 = IOMUX_PAD(0x02C0, 0x0058, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO12_USB1_OTG_PWR = IOMUX_PAD(0x02C0, 0x0058, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO12_SDMA2_EXT_EVENT1 = IOMUX_PAD(0x02C0, 0x0058, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO12_CCM_OUT1 = IOMUX_PAD(0x02C0, 0x0058, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO13_GPIO1_IO13 = IOMUX_PAD(0x02C4, 0x005C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO13_USB1_OTG_OC = IOMUX_PAD(0x02C4, 0x005C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO13_PWM2_OUT = IOMUX_PAD(0x02C4, 0x005C, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO13_CCM_OUT2 = IOMUX_PAD(0x02C4, 0x005C, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO14_GPIO1_IO14 = IOMUX_PAD(0x02C8, 0x0060, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO14_USB2_OTG_PWR = IOMUX_PAD(0x02C8, 0x0060, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO14_USDHC3_CD_B = IOMUX_PAD(0x02C8, 0x0060, 4, 0x0544, 2, 0),
+ IMX8MM_PAD_GPIO1_IO14_PWM3_OUT = IOMUX_PAD(0x02C8, 0x0060, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO14_CCM_CLKO1 = IOMUX_PAD(0x02C8, 0x0060, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO15_GPIO1_IO15 = IOMUX_PAD(0x02CC, 0x0064, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO15_USB2_OTG_OC = IOMUX_PAD(0x02CC, 0x0064, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO15_USDHC3_WP = IOMUX_PAD(0x02CC, 0x0064, 4, 0x0548, 2, 0),
+ IMX8MM_PAD_GPIO1_IO15_PWM4_OUT = IOMUX_PAD(0x02CC, 0x0064, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO15_CCM_CLKO2 = IOMUX_PAD(0x02CC, 0x0064, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_MDC_ENET1_MDC = IOMUX_PAD(0x02D0, 0x0068, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_MDC_GPIO1_IO16 = IOMUX_PAD(0x02D0, 0x0068, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_MDIO_ENET1_MDIO = IOMUX_PAD(0x02D4, 0x006C, 0, 0x04C0, 1, 0),
+ IMX8MM_PAD_ENET_MDIO_GPIO1_IO17 = IOMUX_PAD(0x02D4, 0x006C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_TD3_ENET1_RGMII_TD3 = IOMUX_PAD(0x02D8, 0x0070, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_TD3_GPIO1_IO18 = IOMUX_PAD(0x02D8, 0x0070, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_TD2_ENET1_RGMII_TD2 = IOMUX_PAD(0x02DC, 0x0074, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_TD2_ENET1_TX_CLK = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_TD2_CCM_ENET_REF_CLK_ROOT = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_TD2_GPIO1_IO19 = IOMUX_PAD(0x02DC, 0x0074, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_TD1_ENET1_RGMII_TD1 = IOMUX_PAD(0x02E0, 0x0078, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_TD1_GPIO1_IO20 = IOMUX_PAD(0x02E0, 0x0078, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_TD0_ENET1_RGMII_TD0 = IOMUX_PAD(0x02E4, 0x007C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_TD0_GPIO1_IO21 = IOMUX_PAD(0x02E4, 0x007C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_TX_CTL_ENET1_RGMII_TX_CTL = IOMUX_PAD(0x02E8, 0x0080, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_TX_CTL_GPIO1_IO22 = IOMUX_PAD(0x02E8, 0x0080, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_TXC_ENET1_RGMII_TXC = IOMUX_PAD(0x02EC, 0x0084, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_TXC_ENET1_TX_ER = IOMUX_PAD(0x02EC, 0x0084, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_TXC_GPIO1_IO23 = IOMUX_PAD(0x02EC, 0x0084, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_RX_CTL_ENET1_RGMII_RX_CTL = IOMUX_PAD(0x02F0, 0x0088, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_RX_CTL_GPIO1_IO24 = IOMUX_PAD(0x02F0, 0x0088, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_RXC_ENET1_RGMII_RXC = IOMUX_PAD(0x02F4, 0x008C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_RXC_ENET1_RX_ER = IOMUX_PAD(0x02F4, 0x008C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_RXC_GPIO1_IO25 = IOMUX_PAD(0x02F4, 0x008C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_RD0_ENET1_RGMII_RD0 = IOMUX_PAD(0x02F8, 0x0090, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_RD0_GPIO1_IO26 = IOMUX_PAD(0x02F8, 0x0090, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_RD1_ENET1_RGMII_RD1 = IOMUX_PAD(0x02FC, 0x0094, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_RD1_GPIO1_IO27 = IOMUX_PAD(0x02FC, 0x0094, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_RD2_ENET1_RGMII_RD2 = IOMUX_PAD(0x0300, 0x0098, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_RD2_GPIO1_IO28 = IOMUX_PAD(0x0300, 0x0098, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_RD3_ENET1_RGMII_RD3 = IOMUX_PAD(0x0304, 0x009C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_RD3_GPIO1_IO29 = IOMUX_PAD(0x0304, 0x009C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_CLK_USDHC1_CLK = IOMUX_PAD(0x0308, 0x00A0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_CLK_GPIO2_IO0 = IOMUX_PAD(0x0308, 0x00A0, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_CMD_USDHC1_CMD = IOMUX_PAD(0x030C, 0x00A4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_CMD_GPIO2_IO1 = IOMUX_PAD(0x030C, 0x00A4, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_DATA0_USDHC1_DATA0 = IOMUX_PAD(0x0310, 0x00A8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_DATA0_GPIO2_IO2 = IOMUX_PAD(0x0310, 0x00A8, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_DATA1_USDHC1_DATA1 = IOMUX_PAD(0x0314, 0x00AC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_DATA1_GPIO2_IO3 = IOMUX_PAD(0x0314, 0x00AC, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_DATA2_USDHC1_DATA2 = IOMUX_PAD(0x0318, 0x00B0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_DATA2_GPIO2_IO4 = IOMUX_PAD(0x0318, 0x00B0, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_DATA3_USDHC1_DATA3 = IOMUX_PAD(0x031C, 0x00B4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_DATA3_GPIO2_IO5 = IOMUX_PAD(0x031C, 0x00B4, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_DATA4_USDHC1_DATA4 = IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_DATA4_GPIO2_IO6 = IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_DATA5_USDHC1_DATA5 = IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_DATA5_GPIO2_IO7 = IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_DATA6_USDHC1_DATA6 = IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_DATA6_GPIO2_IO8 = IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_DATA7_USDHC1_DATA7 = IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_DATA7_GPIO2_IO9 = IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_RESET_B_USDHC1_RESET_B = IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_RESET_B_GPIO2_IO10 = IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_STROBE_USDHC1_STROBE = IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_STROBE_GPIO2_IO11 = IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD2_CD_B_USDHC2_CD_B = IOMUX_PAD(0x0338, 0x00D0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_CD_B_GPIO2_IO12 = IOMUX_PAD(0x0338, 0x00D0, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD2_CLK_USDHC2_CLK = IOMUX_PAD(0x033C, 0x00D4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_CLK_GPIO2_IO13 = IOMUX_PAD(0x033C, 0x00D4, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_CLK_CCM_OBSERVE0 = IOMUX_PAD(0x033C, 0x00D4, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD2_CMD_USDHC2_CMD = IOMUX_PAD(0x0340, 0x00D8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_CMD_GPIO2_IO14 = IOMUX_PAD(0x0340, 0x00D8, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_CMD_CCM_OBSERVE1 = IOMUX_PAD(0x0340, 0x00D8, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 = IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_DATA0_GPIO2_IO15 = IOMUX_PAD(0x0344, 0x00DC, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_DATA0_CCM_OBSERVE2 = IOMUX_PAD(0x0344, 0x00DC, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 = IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_DATA1_GPIO2_IO16 = IOMUX_PAD(0x0348, 0x00E0, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_DATA1_CCM_WAIT = IOMUX_PAD(0x0348, 0x00E0, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 = IOMUX_PAD(0x034C, 0x00E4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_DATA2_GPIO2_IO17 = IOMUX_PAD(0x034C, 0x00E4, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_DATA2_CCM_STOP = IOMUX_PAD(0x034C, 0x00E4, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 = IOMUX_PAD(0x0350, 0x00E8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_DATA3_GPIO2_IO18 = IOMUX_PAD(0x0350, 0x00E8, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_DATA3_SRC_EARLY_RESET = IOMUX_PAD(0x0350, 0x00E8, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD2_RESET_B_USDHC2_RESET_B = IOMUX_PAD(0x0354, 0x00EC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 = IOMUX_PAD(0x0354, 0x00EC, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_RESET_B_SRC_SYSTEM_RESET = IOMUX_PAD(0x0354, 0x00EC, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD2_WP_USDHC2_WP = IOMUX_PAD(0x0358, 0x00F0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_WP_GPIO2_IO20 = IOMUX_PAD(0x0358, 0x00F0, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_ALE_RAWNAND_ALE = IOMUX_PAD(0x035C, 0x00F4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_ALE_QSPI_A_SCLK = IOMUX_PAD(0x035C, 0x00F4, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_ALE_GPIO3_IO0 = IOMUX_PAD(0x035C, 0x00F4, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_CE0_B_RAWNAND_CE0_B = IOMUX_PAD(0x0360, 0x00F8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE0_B_QSPI_A_SS0_B = IOMUX_PAD(0x0360, 0x00F8, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE0_B_GPIO3_IO1 = IOMUX_PAD(0x0360, 0x00F8, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_CE1_B_RAWNAND_CE1_B = IOMUX_PAD(0x0364, 0x00FC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE1_B_QSPI_A_SS1_B = IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE1_B_USDHC3_STROBE = IOMUX_PAD(0x0364, 0x00FC, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE1_B_GPIO3_IO2 = IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_CE2_B_RAWNAND_CE2_B = IOMUX_PAD(0x0368, 0x0100, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE2_B_QSPI_B_SS0_B = IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 = IOMUX_PAD(0x0368, 0x0100, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE2_B_GPIO3_IO3 = IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_CE3_B_RAWNAND_CE3_B = IOMUX_PAD(0x036C, 0x0104, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE3_B_QSPI_B_SS1_B = IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 = IOMUX_PAD(0x036C, 0x0104, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE3_B_GPIO3_IO4 = IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_CLE_RAWNAND_CLE = IOMUX_PAD(0x0370, 0x0108, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CLE_QSPI_B_SCLK = IOMUX_PAD(0x0370, 0x0108, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 = IOMUX_PAD(0x0370, 0x0108, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CLE_GPIO3_IO5 = IOMUX_PAD(0x0370, 0x0108, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_DATA00_RAWNAND_DATA00 = IOMUX_PAD(0x0374, 0x010C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA00_QSPI_A_DATA0 = IOMUX_PAD(0x0374, 0x010C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA00_GPIO3_IO6 = IOMUX_PAD(0x0374, 0x010C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_DATA01_RAWNAND_DATA01 = IOMUX_PAD(0x0378, 0x0110, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA01_QSPI_A_DATA1 = IOMUX_PAD(0x0378, 0x0110, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA01_GPIO3_IO7 = IOMUX_PAD(0x0378, 0x0110, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_DATA02_RAWNAND_DATA02 = IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA02_QSPI_A_DATA2 = IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA02_USDHC3_CD_B = IOMUX_PAD(0x037C, 0x0114, 2, 0x0544, 0, 0),
+ IMX8MM_PAD_NAND_DATA02_GPIO3_IO8 = IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_DATA03_RAWNAND_DATA03 = IOMUX_PAD(0x0380, 0x0118, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA03_QSPI_A_DATA3 = IOMUX_PAD(0x0380, 0x0118, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA03_USDHC3_WP = IOMUX_PAD(0x0380, 0x0118, 2, 0x0548, 0, 0),
+ IMX8MM_PAD_NAND_DATA03_GPIO3_IO9 = IOMUX_PAD(0x0380, 0x0118, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_DATA04_RAWNAND_DATA04 = IOMUX_PAD(0x0384, 0x011C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA04_QSPI_B_DATA0 = IOMUX_PAD(0x0384, 0x011C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 = IOMUX_PAD(0x0384, 0x011C, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA04_GPIO3_IO10 = IOMUX_PAD(0x0384, 0x011C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_DATA05_RAWNAND_DATA05 = IOMUX_PAD(0x0388, 0x0120, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA05_QSPI_B_DATA1 = IOMUX_PAD(0x0388, 0x0120, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 = IOMUX_PAD(0x0388, 0x0120, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA05_GPIO3_IO11 = IOMUX_PAD(0x0388, 0x0120, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_DATA06_RAWNAND_DATA06 = IOMUX_PAD(0x038C, 0x0124, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA06_QSPI_B_DATA2 = IOMUX_PAD(0x038C, 0x0124, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 = IOMUX_PAD(0x038C, 0x0124, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA06_GPIO3_IO12 = IOMUX_PAD(0x038C, 0x0124, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_DATA07_RAWNAND_DATA07 = IOMUX_PAD(0x0390, 0x0128, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA07_QSPI_B_DATA3 = IOMUX_PAD(0x0390, 0x0128, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 = IOMUX_PAD(0x0390, 0x0128, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA07_GPIO3_IO13 = IOMUX_PAD(0x0390, 0x0128, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_DQS_RAWNAND_DQS = IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DQS_QSPI_A_DQS = IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DQS_GPIO3_IO14 = IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_RE_B_RAWNAND_RE_B = IOMUX_PAD(0x0398, 0x0130, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_RE_B_QSPI_B_DQS = IOMUX_PAD(0x0398, 0x0130, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 = IOMUX_PAD(0x0398, 0x0130, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_RE_B_GPIO3_IO15 = IOMUX_PAD(0x0398, 0x0130, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_READY_B_RAWNAND_READY_B = IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_READY_B_USDHC3_RESET_B = IOMUX_PAD(0x039C, 0x0134, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_READY_B_GPIO3_IO16 = IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_WE_B_RAWNAND_WE_B = IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_WE_B_USDHC3_CLK = IOMUX_PAD(0x03A0, 0x0138, 2 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_WE_B_GPIO3_IO17 = IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_WP_B_RAWNAND_WP_B = IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_WP_B_USDHC3_CMD = IOMUX_PAD(0x03A4, 0x013C, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_WP_B_GPIO3_IO18 = IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI5_RXFS_SAI5_RX_SYNC = IOMUX_PAD(0x03A8, 0x0140, 0, 0x04E4, 0, 0),
+ IMX8MM_PAD_SAI5_RXFS_SAI1_TX_DATA0 = IOMUX_PAD(0x03A8, 0x0140, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI5_RXFS_GPIO3_IO19 = IOMUX_PAD(0x03A8, 0x0140, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI5_RXC_SAI5_RX_BCLK = IOMUX_PAD(0x03AC, 0x0144, 0, 0x04D0, 0, 0),
+ IMX8MM_PAD_SAI5_RXC_SAI1_TX_DATA1 = IOMUX_PAD(0x03AC, 0x0144, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI5_RXC_PDM_CLK = IOMUX_PAD(0x03AC, 0x0144, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI5_RXC_GPIO3_IO20 = IOMUX_PAD(0x03AC, 0x0144, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI5_RXD0_SAI5_RX_DATA0 = IOMUX_PAD(0x03B0, 0x0148, 0, 0x04D4, 0, 0),
+ IMX8MM_PAD_SAI5_RXD0_SAI1_TX_DATA2 = IOMUX_PAD(0x03B0, 0x0148, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI5_RXD0_PDM_BIT_STREAM0 = IOMUX_PAD(0x03B0, 0x0148, 4, 0x0534, 0, 0),
+ IMX8MM_PAD_SAI5_RXD0_GPIO3_IO21 = IOMUX_PAD(0x03B0, 0x0148, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI5_RXD1_SAI5_RX_DATA1 = IOMUX_PAD(0x03B4, 0x014C, 0, 0x04D8, 0, 0),
+ IMX8MM_PAD_SAI5_RXD1_SAI1_TX_DATA3 = IOMUX_PAD(0x03B4, 0x014C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI5_RXD1_SAI1_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 2, 0x04CC, 0, 0),
+ IMX8MM_PAD_SAI5_RXD1_SAI5_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 3, 0x04EC, 0, 0),
+ IMX8MM_PAD_SAI5_RXD1_PDM_BIT_STREAM1 = IOMUX_PAD(0x03B4, 0x014C, 4, 0x0538, 0, 0),
+ IMX8MM_PAD_SAI5_RXD1_GPIO3_IO22 = IOMUX_PAD(0x03B4, 0x014C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI5_RXD2_SAI5_RX_DATA2 = IOMUX_PAD(0x03B8, 0x0150, 0, 0x04DC, 0, 0),
+ IMX8MM_PAD_SAI5_RXD2_SAI1_TX_DATA4 = IOMUX_PAD(0x03B8, 0x0150, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI5_RXD2_SAI1_TX_SYNC = IOMUX_PAD(0x03B8, 0x0150, 2, 0x04CC, 1, 0),
+ IMX8MM_PAD_SAI5_RXD2_SAI5_TX_BCLK = IOMUX_PAD(0x03B8, 0x0150, 3, 0x04E8, 0, 0),
+ IMX8MM_PAD_SAI5_RXD2_PDM_BIT_STREAM2 = IOMUX_PAD(0x03B8, 0x0150, 4, 0x053C, 0, 0),
+ IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23 = IOMUX_PAD(0x03B8, 0x0150, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI5_RXD3_SAI5_RX_DATA3 = IOMUX_PAD(0x03BC, 0x0154, 0, 0x04E0, 0, 0),
+ IMX8MM_PAD_SAI5_RXD3_SAI1_TX_DATA5 = IOMUX_PAD(0x03BC, 0x0154, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI5_RXD3_SAI1_TX_SYNC = IOMUX_PAD(0x03BC, 0x0154, 2, 0x04CC, 2, 0),
+ IMX8MM_PAD_SAI5_RXD3_SAI5_TX_DATA0 = IOMUX_PAD(0x03BC, 0x0154, 3, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI5_RXD3_PDM_BIT_STREAM3 = IOMUX_PAD(0x03BC, 0x0154, 4, 0x0540, 0, 0),
+ IMX8MM_PAD_SAI5_RXD3_GPIO3_IO24 = IOMUX_PAD(0x03BC, 0x0154, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI5_MCLK_SAI5_MCLK = IOMUX_PAD(0x03C0, 0x0158, 0, 0x052C, 0, 0),
+ IMX8MM_PAD_SAI5_MCLK_SAI1_TX_BCLK = IOMUX_PAD(0x03C0, 0x0158, 1, 0x04C8, 0, 0),
+ IMX8MM_PAD_SAI5_MCLK_GPIO3_IO25 = IOMUX_PAD(0x03C0, 0x0158, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI5_MCLK_SRC_TESTER_ACK = IOMUX_PAD(0x03C0, 0x0158, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_RXFS_SAI1_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 0, 0x04C4, 0, 0),
+ IMX8MM_PAD_SAI1_RXFS_SAI5_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 1, 0x04E4, 1, 0),
+ IMX8MM_PAD_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK = IOMUX_PAD(0x03C4, 0x015C, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXFS_GPIO4_IO0 = IOMUX_PAD(0x03C4, 0x015C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_RXC_SAI1_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXC_SAI5_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 1, 0x04D0, 1, 0),
+ IMX8MM_PAD_SAI1_RXC_ARM_PLATFORM_TRACE_CTL = IOMUX_PAD(0x03C8, 0x0160, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXC_GPIO4_IO1 = IOMUX_PAD(0x03C8, 0x0160, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_RXD0_SAI1_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD0_SAI5_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 1, 0x04D4, 1, 0),
+ IMX8MM_PAD_SAI1_RXD0_SAI1_TX_DATA1 = IOMUX_PAD(0x03CC, 0x0164, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD0_PDM_BIT_STREAM0 = IOMUX_PAD(0x03CC, 0x0164, 3, 0x0534, 1, 0),
+ IMX8MM_PAD_SAI1_RXD0_ARM_PLATFORM_TRACE0 = IOMUX_PAD(0x03CC, 0x0164, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD0_GPIO4_IO2 = IOMUX_PAD(0x03CC, 0x0164, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD0_SRC_BOOT_CFG0 = IOMUX_PAD(0x03CC, 0x0164, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_RXD1_SAI1_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD1_SAI5_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 1, 0x04D8, 1, 0),
+ IMX8MM_PAD_SAI1_RXD1_PDM_BIT_STREAM1 = IOMUX_PAD(0x03D0, 0x0168, 3, 0x0538, 1, 0),
+ IMX8MM_PAD_SAI1_RXD1_ARM_PLATFORM_TRACE1 = IOMUX_PAD(0x03D0, 0x0168, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD1_GPIO4_IO3 = IOMUX_PAD(0x03D0, 0x0168, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD1_SRC_BOOT_CFG1 = IOMUX_PAD(0x03D0, 0x0168, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_RXD2_SAI1_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD2_SAI5_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 1, 0x04DC, 1, 0),
+ IMX8MM_PAD_SAI1_RXD2_PDM_BIT_STREAM2 = IOMUX_PAD(0x03D4, 0x016C, 3, 0x053C, 1, 0),
+ IMX8MM_PAD_SAI1_RXD2_ARM_PLATFORM_TRACE2 = IOMUX_PAD(0x03D4, 0x016C, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD2_GPIO4_IO4 = IOMUX_PAD(0x03D4, 0x016C, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD2_SRC_BOOT_CFG2 = IOMUX_PAD(0x03D4, 0x016C, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_RXD3_SAI1_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD3_SAI5_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 1, 0x04E0, 1, 0),
+ IMX8MM_PAD_SAI1_RXD3_PDM_BIT_STREAM3 = IOMUX_PAD(0x03D8, 0x0170, 3, 0x0540, 1, 0),
+ IMX8MM_PAD_SAI1_RXD3_ARM_PLATFORM_TRACE3 = IOMUX_PAD(0x03D8, 0x0170, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD3_GPIO4_IO5 = IOMUX_PAD(0x03D8, 0x0170, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD3_SRC_BOOT_CFG3 = IOMUX_PAD(0x03D8, 0x0170, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_RXD4_SAI1_RX_DATA4 = IOMUX_PAD(0x03DC, 0x0174, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD4_SAI6_TX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 1, 0x051C, 0, 0),
+ IMX8MM_PAD_SAI1_RXD4_SAI6_RX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 2, 0x0510, 0, 0),
+ IMX8MM_PAD_SAI1_RXD4_ARM_PLATFORM_TRACE4 = IOMUX_PAD(0x03DC, 0x0174, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD4_GPIO4_IO6 = IOMUX_PAD(0x03DC, 0x0174, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD4_SRC_BOOT_CFG4 = IOMUX_PAD(0x03DC, 0x0174, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_RXD5_SAI1_RX_DATA5 = IOMUX_PAD(0x03E0, 0x0178, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD5_SAI6_TX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD5_SAI6_RX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 2, 0x0514, 0, 0),
+ IMX8MM_PAD_SAI1_RXD5_SAI1_RX_SYNC = IOMUX_PAD(0x03E0, 0x0178, 3, 0x04C4, 1, 0),
+ IMX8MM_PAD_SAI1_RXD5_ARM_PLATFORM_TRACE5 = IOMUX_PAD(0x03E0, 0x0178, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD5_GPIO4_IO7 = IOMUX_PAD(0x03E0, 0x0178, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD5_SRC_BOOT_CFG5 = IOMUX_PAD(0x03E0, 0x0178, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_RXD6_SAI1_RX_DATA6 = IOMUX_PAD(0x03E4, 0x017C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD6_SAI6_TX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 1, 0x0520, 0, 0),
+ IMX8MM_PAD_SAI1_RXD6_SAI6_RX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 2, 0x0518, 0, 0),
+ IMX8MM_PAD_SAI1_RXD6_ARM_PLATFORM_TRACE6 = IOMUX_PAD(0x03E4, 0x017C, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD6_GPIO4_IO8 = IOMUX_PAD(0x03E4, 0x017C, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD6_SRC_BOOT_CFG6 = IOMUX_PAD(0x03E4, 0x017C, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_RXD7_SAI1_RX_DATA7 = IOMUX_PAD(0x03E8, 0x0180, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD7_SAI6_MCLK = IOMUX_PAD(0x03E8, 0x0180, 1, 0x0530, 0, 0),
+ IMX8MM_PAD_SAI1_RXD7_SAI1_TX_SYNC = IOMUX_PAD(0x03E8, 0x0180, 2, 0x04CC, 4, 0),
+ IMX8MM_PAD_SAI1_RXD7_SAI1_TX_DATA4 = IOMUX_PAD(0x03E8, 0x0180, 3, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD7_ARM_PLATFORM_TRACE7 = IOMUX_PAD(0x03E8, 0x0180, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD7_GPIO4_IO9 = IOMUX_PAD(0x03E8, 0x0180, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD7_SRC_BOOT_CFG7 = IOMUX_PAD(0x03E8, 0x0180, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_TXFS_SAI1_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 0, 0x04CC, 3, 0),
+ IMX8MM_PAD_SAI1_TXFS_SAI5_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 1, 0x04EC, 1, 0),
+ IMX8MM_PAD_SAI1_TXFS_ARM_PLATFORM_EVENTO = IOMUX_PAD(0x03EC, 0x0184, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXFS_GPIO4_IO10 = IOMUX_PAD(0x03EC, 0x0184, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_TXC_SAI1_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 0, 0x04C8, 1, 0),
+ IMX8MM_PAD_SAI1_TXC_SAI5_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 1, 0x04E8, 1, 0),
+ IMX8MM_PAD_SAI1_TXC_ARM_PLATFORM_EVENTI = IOMUX_PAD(0x03F0, 0x0188, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXC_GPIO4_IO11 = IOMUX_PAD(0x03F0, 0x0188, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_TXD0_SAI1_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD0_SAI5_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD0_ARM_PLATFORM_TRACE8 = IOMUX_PAD(0x03F4, 0x018C, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD0_GPIO4_IO12 = IOMUX_PAD(0x03F4, 0x018C, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD0_SRC_BOOT_CFG8 = IOMUX_PAD(0x03F4, 0x018C, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_TXD1_SAI1_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD1_SAI5_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD1_ARM_PLATFORM_TRACE9 = IOMUX_PAD(0x03F8, 0x0190, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD1_GPIO4_IO13 = IOMUX_PAD(0x03F8, 0x0190, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD1_SRC_BOOT_CFG9 = IOMUX_PAD(0x03F8, 0x0190, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_TXD2_SAI1_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD2_SAI5_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD2_ARM_PLATFORM_TRACE10 = IOMUX_PAD(0x03FC, 0x0194, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD2_GPIO4_IO14 = IOMUX_PAD(0x03FC, 0x0194, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD2_SRC_BOOT_CFG10 = IOMUX_PAD(0x03FC, 0x0194, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_TXD3_SAI1_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD3_SAI5_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD3_ARM_PLATFORM_TRACE11 = IOMUX_PAD(0x0400, 0x0198, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD3_GPIO4_IO15 = IOMUX_PAD(0x0400, 0x0198, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD3_SRC_BOOT_CFG11 = IOMUX_PAD(0x0400, 0x0198, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_TXD4_SAI1_TX_DATA4 = IOMUX_PAD(0x0404, 0x019C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD4_SAI6_RX_BCLK = IOMUX_PAD(0x0404, 0x019C, 1, 0x0510, 1, 0),
+ IMX8MM_PAD_SAI1_TXD4_SAI6_TX_BCLK = IOMUX_PAD(0x0404, 0x019C, 2, 0x051C, 1, 0),
+ IMX8MM_PAD_SAI1_TXD4_ARM_PLATFORM_TRACE12 = IOMUX_PAD(0x0404, 0x019C, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD4_GPIO4_IO16 = IOMUX_PAD(0x0404, 0x019C, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD4_SRC_BOOT_CFG12 = IOMUX_PAD(0x0404, 0x019C, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_TXD5_SAI1_TX_DATA5 = IOMUX_PAD(0x0408, 0x01A0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD5_SAI6_RX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 1, 0x0514, 1, 0),
+ IMX8MM_PAD_SAI1_TXD5_SAI6_TX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD5_ARM_PLATFORM_TRACE13 = IOMUX_PAD(0x0408, 0x01A0, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD5_GPIO4_IO17 = IOMUX_PAD(0x0408, 0x01A0, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD5_SRC_BOOT_CFG13 = IOMUX_PAD(0x0408, 0x01A0, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_TXD6_SAI1_TX_DATA6 = IOMUX_PAD(0x040C, 0x01A4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD6_SAI6_RX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 1, 0x0518, 1, 0),
+ IMX8MM_PAD_SAI1_TXD6_SAI6_TX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 2, 0x0520, 1, 0),
+ IMX8MM_PAD_SAI1_TXD6_ARM_PLATFORM_TRACE14 = IOMUX_PAD(0x040C, 0x01A4, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD6_GPIO4_IO18 = IOMUX_PAD(0x040C, 0x01A4, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD6_SRC_BOOT_CFG14 = IOMUX_PAD(0x040C, 0x01A4, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_TXD7_SAI1_TX_DATA7 = IOMUX_PAD(0x0410, 0x01A8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD7_SAI6_MCLK = IOMUX_PAD(0x0410, 0x01A8, 1, 0x0530, 1, 0),
+ IMX8MM_PAD_SAI1_TXD7_PDM_CLK = IOMUX_PAD(0x0410, 0x01A8, 3, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD7_ARM_PLATFORM_TRACE15 = IOMUX_PAD(0x0410, 0x01A8, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD7_GPIO4_IO19 = IOMUX_PAD(0x0410, 0x01A8, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD7_SRC_BOOT_CFG15 = IOMUX_PAD(0x0410, 0x01A8, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_MCLK_SAI1_MCLK = IOMUX_PAD(0x0414, 0x01AC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_MCLK_SAI5_MCLK = IOMUX_PAD(0x0414, 0x01AC, 1, 0x052C, 1, 0),
+ IMX8MM_PAD_SAI1_MCLK_SAI1_TX_BCLK = IOMUX_PAD(0x0414, 0x01AC, 2, 0x04C8, 2, 0),
+ IMX8MM_PAD_SAI1_MCLK_PDM_CLK = IOMUX_PAD(0x0414, 0x01AC, 3, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_MCLK_GPIO4_IO20 = IOMUX_PAD(0x0414, 0x01AC, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI2_RXFS_SAI2_RX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_RXFS_SAI5_TX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 1, 0x04EC, 2, 0),
+ IMX8MM_PAD_SAI2_RXFS_SAI5_TX_DATA1 = IOMUX_PAD(0x0418, 0x01B0, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_RXFS_SAI2_RX_DATA1 = IOMUX_PAD(0x0418, 0x01B0, 3, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_RXFS_UART1_TX = IOMUX_PAD(0x0418, 0x01B0, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_RXFS_UART1_RX = IOMUX_PAD(0x0418, 0x01B0, 4, 0x04F4, 2, 0),
+ IMX8MM_PAD_SAI2_RXFS_GPIO4_IO21 = IOMUX_PAD(0x0418, 0x01B0, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI2_RXC_SAI2_RX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_RXC_SAI5_TX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 1, 0x04E8, 2, 0),
+ IMX8MM_PAD_SAI2_RXC_UART1_RX = IOMUX_PAD(0x041C, 0x01B4, 4, 0x04F4, 3, 0),
+ IMX8MM_PAD_SAI2_RXC_UART1_TX = IOMUX_PAD(0x041C, 0x01B4, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_RXC_GPIO4_IO22 = IOMUX_PAD(0x041C, 0x01B4, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI2_RXD0_SAI2_RX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_RXD0_SAI5_TX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_RXD0_UART1_RTS_B = IOMUX_PAD(0x0420, 0x01B8, 4, 0x04F0, 2, 0),
+ IMX8MM_PAD_SAI2_RXD0_UART1_CTS_B = IOMUX_PAD(0x0420, 0x01B8, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_RXD0_GPIO4_IO23 = IOMUX_PAD(0x0420, 0x01B8, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI2_TXFS_SAI2_TX_SYNC = IOMUX_PAD(0x0424, 0x01BC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_TXFS_SAI5_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_TXFS_SAI2_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 3, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_TXFS_UART1_CTS_B = IOMUX_PAD(0x0424, 0x01BC, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_TXFS_UART1_RTS_B = IOMUX_PAD(0x0424, 0x01BC, 4, 0x04F0, 3, 0),
+ IMX8MM_PAD_SAI2_TXFS_GPIO4_IO24 = IOMUX_PAD(0x0424, 0x01BC, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI2_TXC_SAI2_TX_BCLK = IOMUX_PAD(0x0428, 0x01C0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_TXC_SAI5_TX_DATA2 = IOMUX_PAD(0x0428, 0x01C0, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_TXC_GPIO4_IO25 = IOMUX_PAD(0x0428, 0x01C0, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI2_TXD0_SAI2_TX_DATA0 = IOMUX_PAD(0x042C, 0x01C4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_TXD0_SAI5_TX_DATA3 = IOMUX_PAD(0x042C, 0x01C4, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_TXD0_GPIO4_IO26 = IOMUX_PAD(0x042C, 0x01C4, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI2_MCLK_SAI2_MCLK = IOMUX_PAD(0x0430, 0x01C8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_MCLK_SAI5_MCLK = IOMUX_PAD(0x0430, 0x01C8, 1, 0x052C, 2, 0),
+ IMX8MM_PAD_SAI2_MCLK_GPIO4_IO27 = IOMUX_PAD(0x0430, 0x01C8, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI3_RXFS_SAI3_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_RXFS_GPT1_CAPTURE1 = IOMUX_PAD(0x0434, 0x01CC, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_RXFS_SAI5_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 2, 0x04E4, 2, 0),
+ IMX8MM_PAD_SAI3_RXFS_SAI3_RX_DATA1 = IOMUX_PAD(0x0434, 0x01CC, 3, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_RXFS_GPIO4_IO28 = IOMUX_PAD(0x0434, 0x01CC, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI3_RXC_SAI3_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_RXC_GPT1_CLK = IOMUX_PAD(0x0438, 0x01D0, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_RXC_SAI5_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 2, 0x04D0, 2, 0),
+ IMX8MM_PAD_SAI3_RXC_UART2_CTS_B = IOMUX_PAD(0x0438, 0x01D0, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_RXC_UART2_RTS_B = IOMUX_PAD(0x0438, 0x01D0, 4, 0x04F8, 2, 0),
+ IMX8MM_PAD_SAI3_RXC_GPIO4_IO29 = IOMUX_PAD(0x0438, 0x01D0, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI3_RXD_SAI3_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_RXD_GPT1_COMPARE1 = IOMUX_PAD(0x043C, 0x01D4, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_RXD_SAI5_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 2, 0x04D4, 2, 0),
+ IMX8MM_PAD_SAI3_RXD_UART2_RTS_B = IOMUX_PAD(0x043C, 0x01D4, 4, 0x04F8, 3, 0),
+ IMX8MM_PAD_SAI3_RXD_UART2_CTS_B = IOMUX_PAD(0x043C, 0x01D4, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_RXD_GPIO4_IO30 = IOMUX_PAD(0x043C, 0x01D4, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI3_TXFS_SAI3_TX_SYNC = IOMUX_PAD(0x0440, 0x01D8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_TXFS_GPT1_CAPTURE2 = IOMUX_PAD(0x0440, 0x01D8, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_TXFS_SAI5_RX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 2, 0x04D8, 2, 0),
+ IMX8MM_PAD_SAI3_TXFS_SAI3_TX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 3, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_TXFS_UART2_RX = IOMUX_PAD(0x0440, 0x01D8, 4, 0x04FC, 2, 0),
+ IMX8MM_PAD_SAI3_TXFS_UART2_TX = IOMUX_PAD(0x0440, 0x01D8, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_TXFS_GPIO4_IO31 = IOMUX_PAD(0x0440, 0x01D8, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI3_TXC_SAI3_TX_BCLK = IOMUX_PAD(0x0444, 0x01DC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_TXC_GPT1_COMPARE2 = IOMUX_PAD(0x0444, 0x01DC, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_TXC_SAI5_RX_DATA2 = IOMUX_PAD(0x0444, 0x01DC, 2, 0x04DC, 2, 0),
+ IMX8MM_PAD_SAI3_TXC_UART2_TX = IOMUX_PAD(0x0444, 0x01DC, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_TXC_UART2_RX = IOMUX_PAD(0x0444, 0x01DC, 4, 0x04FC, 3, 0),
+ IMX8MM_PAD_SAI3_TXC_GPIO5_IO0 = IOMUX_PAD(0x0444, 0x01DC, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI3_TXD_SAI3_TX_DATA0 = IOMUX_PAD(0x0448, 0x01E0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_TXD_GPT1_COMPARE3 = IOMUX_PAD(0x0448, 0x01E0, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_TXD_SAI5_RX_DATA3 = IOMUX_PAD(0x0448, 0x01E0, 2, 0x04E0, 2, 0),
+ IMX8MM_PAD_SAI3_TXD_GPIO5_IO1 = IOMUX_PAD(0x0448, 0x01E0, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI3_MCLK_SAI3_MCLK = IOMUX_PAD(0x044C, 0x01E4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_MCLK_PWM4_OUT = IOMUX_PAD(0x044C, 0x01E4, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_MCLK_SAI5_MCLK = IOMUX_PAD(0x044C, 0x01E4, 2, 0x052C, 3, 0),
+ IMX8MM_PAD_SAI3_MCLK_GPIO5_IO2 = IOMUX_PAD(0x044C, 0x01E4, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SPDIF_TX_SPDIF1_OUT = IOMUX_PAD(0x0450, 0x01E8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SPDIF_TX_PWM3_OUT = IOMUX_PAD(0x0450, 0x01E8, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SPDIF_TX_GPIO5_IO3 = IOMUX_PAD(0x0450, 0x01E8, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SPDIF_RX_SPDIF1_IN = IOMUX_PAD(0x0454, 0x01EC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SPDIF_RX_PWM2_OUT = IOMUX_PAD(0x0454, 0x01EC, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SPDIF_RX_GPIO5_IO4 = IOMUX_PAD(0x0454, 0x01EC, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK = IOMUX_PAD(0x0458, 0x01F0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SPDIF_EXT_CLK_PWM1_OUT = IOMUX_PAD(0x0458, 0x01F0, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SPDIF_EXT_CLK_GPIO5_IO5 = IOMUX_PAD(0x0458, 0x01F0, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ECSPI1_SCLK_ECSPI1_SCLK = IOMUX_PAD(0x045C, 0x01F4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI1_SCLK_UART3_RX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0),
+ IMX8MM_PAD_ECSPI1_SCLK_UART3_TX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI1_SCLK_GPIO5_IO6 = IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ECSPI1_MOSI_ECSPI1_MOSI = IOMUX_PAD(0x0460, 0x01F8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI1_MOSI_UART3_TX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI1_MOSI_UART3_RX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0),
+ IMX8MM_PAD_ECSPI1_MOSI_GPIO5_IO7 = IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ECSPI1_MISO_ECSPI1_MISO = IOMUX_PAD(0x0464, 0x01FC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI1_MISO_UART3_CTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI1_MISO_UART3_RTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0),
+ IMX8MM_PAD_ECSPI1_MISO_GPIO5_IO8 = IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ECSPI1_SS0_ECSPI1_SS0 = IOMUX_PAD(0x0468, 0x0200, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI1_SS0_UART3_RTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0),
+ IMX8MM_PAD_ECSPI1_SS0_UART3_CTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI1_SS0_GPIO5_IO9 = IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ECSPI2_SCLK_ECSPI2_SCLK = IOMUX_PAD(0x046C, 0x0204, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI2_SCLK_UART4_RX = IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0),
+ IMX8MM_PAD_ECSPI2_SCLK_UART4_TX = IOMUX_PAD(0x046C, 0x0204, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI2_SCLK_GPIO5_IO10 = IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ECSPI2_MOSI_ECSPI2_MOSI = IOMUX_PAD(0x0470, 0x0208, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI2_MOSI_UART4_TX = IOMUX_PAD(0x0470, 0x0208, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI2_MOSI_UART4_RX = IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0),
+ IMX8MM_PAD_ECSPI2_MOSI_GPIO5_IO11 = IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ECSPI2_MISO_ECSPI2_MISO = IOMUX_PAD(0x0474, 0x020C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI2_MISO_UART4_CTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI2_MISO_UART4_RTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0),
+ IMX8MM_PAD_ECSPI2_MISO_GPIO5_IO12 = IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ECSPI2_SS0_ECSPI2_SS0 = IOMUX_PAD(0x0478, 0x0210, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI2_SS0_UART4_RTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0),
+ IMX8MM_PAD_ECSPI2_SS0_UART4_CTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI2_SS0_GPIO5_IO13 = IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_I2C1_SCL_I2C1_SCL = IOMUX_PAD(0x047C, 0x0214, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C1_SCL_ENET1_MDC = IOMUX_PAD(0x047C, 0x0214, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C1_SCL_GPIO5_IO14 = IOMUX_PAD(0x047C, 0x0214, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_I2C1_SDA_I2C1_SDA = IOMUX_PAD(0x0480, 0x0218, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C1_SDA_ENET1_MDIO = IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0),
+ IMX8MM_PAD_I2C1_SDA_GPIO5_IO15 = IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_I2C2_SCL_I2C2_SCL = IOMUX_PAD(0x0484, 0x021C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C2_SCL_ENET1_1588_EVENT1_IN = IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C2_SCL_USDHC3_CD_B = IOMUX_PAD(0x0484, 0x021C, 2, 0x0544, 1, 0),
+ IMX8MM_PAD_I2C2_SCL_GPIO5_IO16 = IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_I2C2_SDA_I2C2_SDA = IOMUX_PAD(0x0488, 0x0220, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C2_SDA_ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C2_SDA_USDHC3_WP = IOMUX_PAD(0x0488, 0x0220, 2, 0x0548, 1, 0),
+ IMX8MM_PAD_I2C2_SDA_GPIO5_IO17 = IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_I2C3_SCL_I2C3_SCL = IOMUX_PAD(0x048C, 0x0224, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C3_SCL_PWM4_OUT = IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C3_SCL_GPT2_CLK = IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C3_SCL_GPIO5_IO18 = IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_I2C3_SDA_I2C3_SDA = IOMUX_PAD(0x0490, 0x0228, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C3_SDA_PWM3_OUT = IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C3_SDA_GPT3_CLK = IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C3_SDA_GPIO5_IO19 = IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_I2C4_SCL_I2C4_SCL = IOMUX_PAD(0x0494, 0x022C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C4_SCL_PWM2_OUT = IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C4_SCL_PCIE1_CLKREQ_B = IOMUX_PAD(0x0494, 0x022C, 2, 0x0524, 0, 0),
+ IMX8MM_PAD_I2C4_SCL_GPIO5_IO20 = IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_I2C4_SDA_I2C4_SDA = IOMUX_PAD(0x0498, 0x0230, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C4_SDA_PWM1_OUT = IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C4_SDA_GPIO5_IO21 = IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_UART1_RXD_UART1_RX = IOMUX_PAD(0x049C, 0x0234, 0, 0x04F4, 0, 0),
+ IMX8MM_PAD_UART1_RXD_UART1_TX = IOMUX_PAD(0x049C, 0x0234, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_UART1_RXD_ECSPI3_SCLK = IOMUX_PAD(0x049C, 0x0234, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_UART1_RXD_GPIO5_IO22 = IOMUX_PAD(0x049C, 0x0234, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_UART1_TXD_UART1_TX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_UART1_TXD_UART1_RX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x04F4, 1, 0),
+ IMX8MM_PAD_UART1_TXD_ECSPI3_MOSI = IOMUX_PAD(0x04A0, 0x0238, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_UART1_TXD_GPIO5_IO23 = IOMUX_PAD(0x04A0, 0x0238, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_UART2_RXD_UART2_RX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x04FC, 0, 0),
+ IMX8MM_PAD_UART2_RXD_UART2_TX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_UART2_RXD_ECSPI3_MISO = IOMUX_PAD(0x04A4, 0x023C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_UART2_RXD_GPIO5_IO24 = IOMUX_PAD(0x04A4, 0x023C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_UART2_TXD_UART2_TX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_UART2_TXD_UART2_RX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x04FC, 1, 0),
+ IMX8MM_PAD_UART2_TXD_ECSPI3_SS0 = IOMUX_PAD(0x04A8, 0x0240, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_UART2_TXD_GPIO5_IO25 = IOMUX_PAD(0x04A8, 0x0240, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_UART3_RXD_UART3_RX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0504, 2, 0),
+ IMX8MM_PAD_UART3_RXD_UART3_TX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_UART3_RXD_UART1_CTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_UART3_RXD_UART1_RTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x04F0, 0, 0),
+ IMX8MM_PAD_UART3_RXD_USDHC3_RESET_B = IOMUX_PAD(0x04AC, 0x0244, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_UART3_RXD_GPIO5_IO26 = IOMUX_PAD(0x04AC, 0x0244, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_UART3_TXD_UART3_TX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_UART3_TXD_UART3_RX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0504, 3, 0),
+ IMX8MM_PAD_UART3_TXD_UART1_RTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x04F0, 1, 0),
+ IMX8MM_PAD_UART3_TXD_UART1_CTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_UART3_TXD_USDHC3_VSELECT = IOMUX_PAD(0x04B0, 0x0248, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_UART3_TXD_GPIO5_IO27 = IOMUX_PAD(0x04B0, 0x0248, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_UART4_RXD_UART4_RX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x050C, 2, 0),
+ IMX8MM_PAD_UART4_RXD_UART4_TX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_UART4_RXD_UART2_CTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_UART4_RXD_UART2_RTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x04F8, 0, 0),
+ IMX8MM_PAD_UART4_RXD_PCIE1_CLKREQ_B = IOMUX_PAD(0x04B4, 0x024C, 2, 0x0524, 1, 0),
+ IMX8MM_PAD_UART4_RXD_GPIO5_IO28 = IOMUX_PAD(0x04B4, 0x024C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_UART4_TXD_UART4_TX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_UART4_TXD_UART4_RX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x050C, 3, 0),
+ IMX8MM_PAD_UART4_TXD_UART2_RTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x04F8, 1, 0),
+ IMX8MM_PAD_UART4_TXD_UART2_CTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_UART4_TXD_GPIO5_IO29 = IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0),
+};
+
+static inline void imx8mm_setup_pad(iomux_v3_cfg_t pad)
+{
+ void __iomem *iomux = IOMEM(MX8MM_IOMUXC_BASE_ADDR);
+
+ imx8m_setup_pad(iomux, pad);
+}
+
+#endif
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx8.h b/arch/arm/mach-imx/include/mach/iomux-mx8mq.h
index 9660697..d397e97 100644
--- a/arch/arm/mach-imx/include/mach/iomux-mx8.h
+++ b/arch/arm/mach-imx/include/mach/iomux-mx8mq.h
@@ -8,8 +8,8 @@
#define __MACH_IOMUX_IMX8MQ_H__
#include <mach/iomux-v3.h>
-
-#define PAD_CTL_DSE_3P3V_45_OHM 0b110
+#include <mach/iomux-mx8m.h>
+#include <mach/imx8mq-regs.h>
enum {
IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0 = IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0),
@@ -623,23 +623,11 @@ enum {
IMX8MQ_PAD_UART4_TXD__GPIO5_IO29 = IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0),
};
-static inline void mx8_setup_pad(void __iomem *iomux, iomux_v3_cfg_t pad)
+static inline void imx8mq_setup_pad(iomux_v3_cfg_t pad)
{
- unsigned int flags = 0;
- uint32_t mode = IOMUX_MODE(pad);
-
- if (mode & IOMUX_CONFIG_LPSR) {
- mode &= ~IOMUX_CONFIG_LPSR;
- flags = ZERO_OFFSET_VALID | IMX7_PINMUX_LPSR;
- }
-
- iomux_v3_setup_pad(iomux, flags,
- IOMUX_CTRL_OFS(pad),
- IOMUX_PAD_CTRL_OFS(pad),
- IOMUX_SEL_INPUT_OFS(pad),
- mode,
- IOMUX_PAD_CTRL(pad),
- IOMUX_SEL_INPUT(pad));
+ void __iomem *iomux = IOMEM(MX8MQ_IOMUXC_BASE_ADDR);
+
+ imx8m_setup_pad(iomux, pad);
}
#endif
diff --git a/arch/arm/mach-imx/include/mach/xload.h b/arch/arm/mach-imx/include/mach/xload.h
index 9709b13..dca05aa 100644
--- a/arch/arm/mach-imx/include/mach/xload.h
+++ b/arch/arm/mach-imx/include/mach/xload.h
@@ -5,7 +5,7 @@ int imx53_nand_start_image(void);
int imx6_spi_load_image(int instance, unsigned int flash_offset, void *buf, int len);
int imx6_spi_start_image(int instance);
int imx6_esdhc_start_image(int instance);
-int imx8_esdhc_load_image(int instance, bool start);
+int imx8m_esdhc_load_image(int instance, bool start);
int imx_image_size(void);
int piggydata_size(void);