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author | Ahmad Fatoum <a.fatoum@pengutronix.de> | 2021-03-24 09:23:02 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-03-29 09:56:52 +0200 |
commit | fef19e17f651a7f4b6063a76c506a67cabfe4a69 (patch) | |
tree | e0e7b011a8d29949b700f13036fe56fbee3633c1 /arch | |
parent | 610720857348a147fad3e330180b1fdf63453f25 (diff) | |
download | barebox-fef19e17f651a7f4b6063a76c506a67cabfe4a69.tar.gz barebox-fef19e17f651a7f4b6063a76c506a67cabfe4a69.tar.xz |
RISC-V: cpu: request stack memory region
Now that the stack base region is determined dynamically,
mem_malloc_resource can no longer reserve the stack space.
Do as ARM does and add a RISC-V specific initcall to reserve
the main thread's stack space.
Reported-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/riscv/cpu/core.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/riscv/cpu/core.c b/arch/riscv/cpu/core.c index bdcd500ed7..982d378edd 100644 --- a/arch/riscv/cpu/core.c +++ b/arch/riscv/cpu/core.c @@ -2,6 +2,9 @@ /* * Copyright (C) 2012 Regents of the University of California * Copyright (C) 2017 SiFive + * Copyright (C) 2021 Ahmad Fatoum, Pengutronix + * + * Common RISC-V core initcalls. * * All RISC-V systems have a timer attached to every hart. These timers can * either be read from the "time" and "timeh" CSRs, and can use the SBI to @@ -14,8 +17,17 @@ #include <of.h> #include <linux/clk.h> #include <linux/err.h> +#include <memory.h> +#include <asm-generic/memory_layout.h> #include <io.h> +static int riscv_request_stack(void) +{ + extern unsigned long riscv_stack_top; + return PTR_ERR_OR_ZERO(request_sdram_region("stack", riscv_stack_top - STACK_SIZE, STACK_SIZE)); +} +coredevice_initcall(riscv_request_stack); + static struct device_d timer_dev; static int riscv_probe(struct device_d *parent) |