Using correct board names all over the place

Signed-off-by: Juergen Beisert <jbe@pengutronix.de>

5 files changed, 311 insertions, 0 deletions

diff --git a/board/pcm037/Makefile b/board/pcm037/Makefile
new file mode 100644
index 0000000000..7d36b77df0
--- /dev/null
+++ b/board/pcm037/Makefile
@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+obj-y += lowlevel_init.o
+obj-y += pcm037.o
diff --git a/board/pcm037/env/bin/init b/board/pcm037/env/bin/init
new file mode 100644
index 0000000000..b75a9af2df
--- /dev/null
+++ b/board/pcm037/env/bin/init
@@ -0,0 +1,12 @@
+#
+# setup the partitions in the main flash
+#
+nor_parts="nor0:128k(uboot),128k(env),2M(kernel),-(jffs2)"
+addpart $nor_parts
+
+#
+# setup default ethernet address
+#
+eth0.ethaddr=80:81:82:83:84:85
+
+echo "System is up and running"
diff --git a/board/pcm037/lowlevel_init.S b/board/pcm037/lowlevel_init.S
new file mode 100644
index 0000000000..12fe5fa7ef
--- /dev/null
+++ b/board/pcm037/lowlevel_init.S
@@ -0,0 +1,113 @@
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/imx-regs.h>
+
+.macro REG reg, val
+	ldr r2, =\reg
+	ldr r3, =\val
+	str r3, [r2]
+.endm
+
+.macro REG8 reg, val
+	ldr r2, =\reg
+	ldr r3, =\val
+	strb r3, [r2]
+.endm
+
+.macro DELAY loops
+	ldr r2, =\loops
+1:
+	subs	r2, r2, #1
+	nop
+	bcs 1b
+.endm
+
+.globl board_init_lowlevel
+board_init_lowlevel:
+
+	REG	IPU_CONF, IPU_CONF_DI_EN
+	REG	CCM_CCMR, 0x074B0BF5
+
+	DELAY 0x40000
+
+	REG	CCM_CCMR, 0x074B0BF5 | CCMR_MPE
+	REG	CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
+
+	REG	CCM_PDR0, PDR0_CSI_PODF(0xff1) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |	PDR0_MCU_PODF(0)
+
+	REG	CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd)
+
+	REG	CCM_SPCTL, PLL_PD(1) | PLL_MFD(0x43) | PLL_MFI(12) | PLL_MFN(1)
+
+	/* Skip SDRAM initialization if we run from RAM */
+	cmp	pc, #0x80000000
+	bls	1f
+	cmp	pc, #0x90000000
+	bhi	1f
+
+	mov	pc, lr
+
+1:
+	REG	0x43FAC26C, 0 /* SDCLK */
+	REG	0x43FAC270, 0 /* CAS */
+	REG	0x43FAC274, 0 /* RAS */
+	REG	0x43FAC27C, 0x1000 /* CS2 	CSD0) */
+	REG	0x43FAC284, 0 /* DQM3 */
+	REG	0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 	0x288..0x2DC) */
+	REG	0x43FAC28C, 0
+	REG	0x43FAC290, 0
+	REG	0x43FAC294, 0
+	REG	0x43FAC298, 0
+	REG	0x43FAC29C, 0
+	REG	0x43FAC2A0, 0
+	REG	0x43FAC2A4, 0
+	REG	0x43FAC2A8, 0
+	REG	0x43FAC2AC, 0
+	REG	0x43FAC2B0, 0
+	REG	0x43FAC2B4, 0
+	REG	0x43FAC2B8, 0
+	REG	0x43FAC2BC, 0
+	REG	0x43FAC2C0, 0
+	REG	0x43FAC2C4, 0
+	REG	0x43FAC2C8, 0
+	REG	0x43FAC2CC, 0
+	REG	0x43FAC2D0, 0
+	REG	0x43FAC2D4, 0
+	REG	0x43FAC2D8, 0
+	REG	0x43FAC2DC, 0
+	REG	0xB8001010, 0x00000004
+	REG	0xB8001004, 0x006ac73a
+	REG	0xB8001000, 0x92100000
+	REG	0x80000f00, 0x12344321
+	REG	0xB8001000, 0xa2100000
+	REG	0x80000000, 0x12344321
+	REG	0x80000000, 0x12344321
+	REG	0xB8001000, 0xb2100000
+	REG8	0x80000033, 0xda
+	REG8	0x81000000, 0xff
+	REG	0xB8001000, 0x82226080
+	REG	0x80000000, 0xDEADBEEF
+	REG	0xB8001010, 0x0000000c
+
+	mov	pc, lr
diff --git a/board/pcm037/pcm037.c b/board/pcm037/pcm037.c
new file mode 100644
index 0000000000..8f39e42d63
--- /dev/null
+++ b/board/pcm037/pcm037.c
@@ -0,0 +1,151 @@
+/*
+ * (C) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Board support for Phytec's, i.MX31 based CPU card, called: PCM037
+ */
+
+#include <common.h>
+#include <init.h>
+#include <driver.h>
+#include <environment.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/gpio.h>
+#include <asm/io.h>
+#include <partition.h>
+
+/*
+ * Up to 64MiB NOR type flash, connected to
+ * CS line 0, data width is 16 bit
+ */
+static struct device_d cfi_dev = {
+	.name     = "cfi_flash",
+	.id       = "nor0",
+	.map_base = IMX_CS0_BASE,
+	.size     = IMX_CS0_RANGE,	/* area size */
+};
+
+/*
+ * up to 2MiB static RAM type memory, connected
+ * to CS4, data width is 16 bit
+ */
+static struct device_d sram_dev = {
+	.name     = "sram",
+	.id       = "sram0",
+	.map_base = IMX_CS4_BASE,
+	.size     = IMX_CS4_RANGE,	/* area size */
+};
+
+/*
+ * ?MiB NAND type flash, data width 8 bit
+ */
+static struct device_d nand_dev = {
+	.name     = "cfi_flash_nand",
+	.id       = "nand0",
+	.map_base = 0x10000000,	/* FIXME */
+	.size     = 16 * 1024 * 1024,	/* FIXME */
+};
+
+/*
+ * SMSC 9217 network controller
+ * connected to CS line 1 and interrupt line
+ * GPIO3, data width is 16 bit
+ */
+static struct device_d network_dev = {
+	.name     = "smc911x",
+	.id       = "eth0",
+	.map_base = IMX_CS1_BASE,
+	.size     = IMX_CS1_RANGE,	/* area size */
+	.type     = DEVICE_TYPE_ETHER,
+};
+
+/*
+ * 128MiB of SDRAM, data width is 32 bit
+ */
+static struct device_d sdram_dev = {
+	.name     = "ram",
+	.id       = "ram0",
+
+	.map_base = IMX_SDRAM_CS0,
+	.size     = 128 * 1024 * 1024,	/* fix size */
+
+	.type     = DEVICE_TYPE_DRAM,
+};
+
+static int imx31_devices_init(void)
+{
+	__REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */
+	__REG(CSCR_L(0)) = 0x10000d03;
+	__REG(CSCR_A(0)) = 0x00720900;
+
+	__REG(CSCR_U(1)) = 0x0000df06; /* CS1: Network Controller */
+	__REG(CSCR_L(1)) = 0x444a4541;
+	__REG(CSCR_A(1)) = 0x44443302;
+
+	__REG(CSCR_U(4)) = 0x0000d843; /* CS4: SRAM */
+	__REG(CSCR_L(4)) = 0x22252521;
+	__REG(CSCR_A(4)) = 0x22220a00;
+
+	/* setup pins for I2C2 (for EEPROM, RTC) */
+	imx_gpio_mode(MUX_CSPI2_MOSI_I2C2_SCL);
+	imx_gpio_mode(MUX_CSPI2_MISO_I2C2_SCL);
+
+	register_device(&cfi_dev);
+
+	/*
+	 * Create partitions that should be
+	 * not touched by any regular user
+	 */
+	dev_add_partition(&cfi_dev, 0x00000, 0x20000, PARTITION_FIXED, "self");	/* ourself */
+	dev_add_partition(&cfi_dev, 0x20000, 0x20000, PARTITION_FIXED, "env");	/* environment */
+	dev_protect(&cfi_dev, 0x20000, 0, 1);
+
+	register_device(&sram_dev);
+	register_device(&nand_dev);
+	register_device(&network_dev);
+
+	register_device(&sdram_dev);
+
+	return 0;
+}
+
+device_initcall(imx31_devices_init);
+
+static struct device_d imx31_serial_device = {
+	.name     = "imx_serial",
+	.id       = "cs0",
+	.map_base = IMX_UART1_BASE,
+	.size     = 16 * 1024,
+	.type     = DEVICE_TYPE_CONSOLE,
+};
+
+static int imx31_console_init(void)
+{
+	/* init gpios for serial port */
+	imx_gpio_mode(MUX_RXD1_UART1_RXD_MUX);
+	imx_gpio_mode(MUX_TXD1_UART1_TXD_MUX);
+	imx_gpio_mode(MUX_RTS1_UART1_RTS_B);
+	imx_gpio_mode(MUX_RTS1_UART1_CTS_B);
+
+	register_device(&imx31_serial_device);
+	return 0;
+}
+
+console_initcall(imx31_console_init);
diff --git a/board/pcm037/pcm037.dox b/board/pcm037/pcm037.dox
new file mode 100644
index 0000000000..b2afdd6acd
--- /dev/null
+++ b/board/pcm037/pcm037.dox
@@ -0,0 +1,11 @@
+/** @page pcm037 Phytec's phyCORE-i.MX31
+
+This CPU card is based on a Freescale i.MX31 CPU. The card is shipped with:
+
+- up to 64MiB NOR type Flash Memory
+- up to 2MiB static RAM
+- 64MiB NAND type Flash Memory
+- SMSC 9217 network controller
+- 128MiB synchronous dynamic RAM
+
+*/