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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2008-10-07 13:14:40 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2008-10-07 13:14:40 +0200 |
| commit | 2a7bcf110f3d6859001c54e78ca81b25d88c4f19 (patch) | |
| tree | b467a790da7c06502ff66ab9fe3c3a89e5eabb43 /board | |
| parent | c3ed0879ba2eb35d67224d3bf93deacc1a756cc9 (diff) | |
| download | barebox-2a7bcf110f3d6859001c54e78ca81b25d88c4f19.tar.gz barebox-2a7bcf110f3d6859001c54e78ca81b25d88c4f19.tar.xz | |
OMAP: SDRC MCFG Register configuration corrected for SDP3430.
Signed-off-by: Shankarganesh K <shankarganesh@ti.com>
Acked-By: Nishanth Menon <nm@ti.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'board')
| -rw-r--r-- | board/omap/board-sdp343x.c | 45 |
1 files changed, 13 insertions, 32 deletions
diff --git a/board/omap/board-sdp343x.c b/board/omap/board-sdp343x.c index f53a8cfb60..130e6cec20 100644 --- a/board/omap/board-sdp343x.c +++ b/board/omap/board-sdp343x.c @@ -85,13 +85,12 @@ void board_init(void) */ static void sdrc_init(void) { - /* issues software reset of SDRAM interface */ - /* No idle ack and RESET enable */ - __raw_writel(0x0A, SDRC_REG(SYSCONFIG)); - sdelay(100); - /* No idle ack and RESET disable */ - __raw_writel(0x08, SDRC_REG(SYSCONFIG)); - + /* Issue SDRC Soft reset */ + __raw_writel(0x12, SDRC_REG(SYSCONFIG)); + /* Wait until Reset complete */ + while ((__raw_readl(SDRC_REG(STATUS)) & 0x1) == 0); + /* SDRC to normal mode */ + __raw_writel(0x10, SDRC_REG(SYSCONFIG)); /* SDRC Sharing register */ /* 32-bit SDRAM on data lane [31:0] - CS0 */ /* pin tri-stated = 1 */ @@ -99,7 +98,7 @@ static void sdrc_init(void) /* ----- SDRC_REG(CS0 Configuration --------- */ /* SDRC_REG(MCFG0 register */ - __raw_writel(0x02D04011, SDRC_REG(MCFG_0)); + __raw_writel(0x02584019, SDRC_REG(MCFG_0)); /* SDRC_REG(RFR_CTRL0 register */ __raw_writel(0x0003DE01, SDRC_REG(RFR_CTRL_0)); @@ -124,35 +123,17 @@ static void sdrc_init(void) __raw_writel(0x00000002, SDRC_REG(MANUAL_0)); /* SDRC MR0 register */ - __raw_writel(0x00000032, SDRC_REG(MR_0)); /* Burst length =4 */ - /* CAS latency = 3 */ /* Write Burst = Read Burst */ /* Serial Mode */ + __raw_writel(0x00000032, SDRC_REG(MR_0)); /* Burst length =4 */ - /* SDRC DLLA control register */ - /* Enable DLL, Load counter with 115 (middle of range) */ - /* Delay is 90 degrees */ - __raw_writel(0x0000730E, SDRC_REG(DLLA_CTRL)); - - /* - * Clear the enable DLL bit to use DLLA in unlock mode - * (counter value is continuously asserted) - */ - __raw_writel(0x0000730A, SDRC_REG(DLLA_CTRL)); - - /* SDRC DLLB control register - * Enable DLL, Load counter with 128 (middle of range) - * Delay is 90 degrees - */ - __raw_writel(0x0000730E, SDRC_REG(DLLB_CTRL)); - - /* - * Clear the enable DLL bit to use DLLB in unlock mode - * (counter value is continuously asserted) - */ - __raw_writel(0x0000730A, SDRC_REG(DLLB_CTRL)); + /* SDRC DLLA control register */ + /* Enable DLL A */ + __raw_writel(0x0000000A, SDRC_REG(DLLA_CTRL)); + /* wait until DLL is locked */ + while ((__raw_readl(SDRC_REG(DLLA_STATUS)) & 0x4) == 0); return; } |