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author | Sascha Hauer <s.hauer@pengutronix.de> | 2009-02-06 14:22:15 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2009-02-06 14:44:46 +0100 |
commit | 612c27f97e039e17811b47d39932e35de25d4f2d (patch) | |
tree | 4061def8184ee153328bedc3580b48452430e12d /board | |
parent | 0cb4c4e2a56ab2a153fe277ee2793512a58621f3 (diff) | |
download | barebox-612c27f97e039e17811b47d39932e35de25d4f2d.tar.gz barebox-612c27f97e039e17811b47d39932e35de25d4f2d.tar.xz |
ARM: Add cache-l2x0 definitions
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'board')
-rw-r--r-- | board/pcm043/pcm043.c | 101 |
1 files changed, 97 insertions, 4 deletions
diff --git a/board/pcm043/pcm043.c b/board/pcm043/pcm043.c index 60e8480e02..cc241a3180 100644 --- a/board/pcm043/pcm043.c +++ b/board/pcm043/pcm043.c @@ -34,6 +34,13 @@ #include <asm/mach-types.h> #include <asm/arch/imx-nand.h> #include <fec.h> +#include "redboot.h" + +#define CYG_MACRO_START +#define CYG_MACRO_END +#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2 +#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \ + (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2)) /* * Up to 32MiB NOR type flash, connected to @@ -81,9 +88,10 @@ static struct device_d nand_dev = { static int imx35_devices_init(void) { - __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash from pcm037*/ - __REG(CSCR_L(0)) = 0x10000d03; - __REG(CSCR_A(0)) = 0x00720900; + /* CS0: Nor Flash */ + writel(0x0000cf03, CSCR_U(0)); + writel(0x10000d03, CSCR_L(0)); + writel(0x00720900, CSCR_A(0)); /* setup pins for I2C1 (for EEPROM, RTC) */ imx_gpio_mode(MUX_I2C1_CLK_I2C1_SLC); @@ -125,7 +133,7 @@ static int imx35_devices_init(void) register_device(&fec_dev); register_device(&sdram0_dev); - + armlinux_set_bootparams((void *)0x80000100); armlinux_set_architecture(MACH_TYPE_PCM043); @@ -155,3 +163,88 @@ static int imx35_console_init(void) } console_initcall(imx35_console_init); + +static int pcm043_core_setup(void) +{ + u32 tmp; + + /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/ + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + writel(0x77777777, IMX_AIPS1_BASE); + writel(0x77777777, IMX_AIPS1_BASE + 0x4); + writel(0x77777777, IMX_AIPS2_BASE); + writel(0x77777777, IMX_AIPS2_BASE + 0x4); + + /* + * Clear the on and off peripheral modules Supervisor Protect bit + * for SDMA to access them. Did not change the AIPS control registers + * (offset 0x20) access type + */ + writel(0x0, IMX_AIPS1_BASE + 0x40); + writel(0x0, IMX_AIPS1_BASE + 0x44); + writel(0x0, IMX_AIPS1_BASE + 0x48); + writel(0x0, IMX_AIPS1_BASE + 0x4C); + tmp = readl(IMX_AIPS1_BASE + 0x50); + tmp &= 0x00FFFFFF; + writel(tmp, IMX_AIPS1_BASE + 0x50); + + writel(0x0, IMX_AIPS2_BASE + 0x40); + writel(0x0, IMX_AIPS2_BASE + 0x44); + writel(0x0, IMX_AIPS2_BASE + 0x48); + writel(0x0, IMX_AIPS2_BASE + 0x4C); + tmp = readl(IMX_AIPS2_BASE + 0x50); + tmp &= 0x00FFFFFF; + writel(tmp, IMX_AIPS2_BASE + 0x50); + + /* MAX (Multi-Layer AHB Crossbar Switch) setup */ + + /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ +#define MAX_PARAM1 0x00302154 + writel(MAX_PARAM1, IMX_MAX_BASE + 0x0); /* for S0 */ + writel(MAX_PARAM1, IMX_MAX_BASE + 0x100); /* for S1 */ + writel(MAX_PARAM1, IMX_MAX_BASE + 0x200); /* for S2 */ + writel(MAX_PARAM1, IMX_MAX_BASE + 0x300); /* for S3 */ + writel(MAX_PARAM1, IMX_MAX_BASE + 0x400); /* for S4 */ + + /* SGPCR - always park on last master */ + writel(0x10, IMX_MAX_BASE + 0x10); /* for S0 */ + writel(0x10, IMX_MAX_BASE + 0x110); /* for S1 */ + writel(0x10, IMX_MAX_BASE + 0x210); /* for S2 */ + writel(0x10, IMX_MAX_BASE + 0x310); /* for S3 */ + writel(0x10, IMX_MAX_BASE + 0x410); /* for S4 */ + + /* MGPCR - restore default values */ + writel(0x0, IMX_MAX_BASE + 0x800); /* for M0 */ + writel(0x0, IMX_MAX_BASE + 0x900); /* for M1 */ + writel(0x0, IMX_MAX_BASE + 0xa00); /* for M2 */ + writel(0x0, IMX_MAX_BASE + 0xb00); /* for M3 */ + writel(0x0, IMX_MAX_BASE + 0xc00); /* for M4 */ + writel(0x0, IMX_MAX_BASE + 0xd00); /* for M5 */ + + writel(0x0000DCF6, CSCR_U(0)); /* CS0: NOR Flash */ + writel(0x444A4541, CSCR_L(0)); + writel(0x44443302, CSCR_A(0)); + + /* + * M3IF Control Register (M3IFCTL) + * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 + * MRRP[1] = MAX1 not on priority list (0 << 0) = 0x00000000 + * MRRP[2] = L2CC1 not on priority list (0 << 0) = 0x00000000 + * MRRP[3] = USB not on priority list (0 << 0) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 + * MRRP[5] = GPU not on priority list (0 << 0) = 0x00000000 + * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 + * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 + * ------------ + * 0x00000040 + */ + writel(0x40, IMX_M3IF_BASE); + + return 0; +} + +core_initcall(pcm043_core_setup); + |