diff options
| author | Sascha Hauer <s.hauer@pengutronix.de> | 2008-09-09 17:06:01 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2008-09-09 17:06:01 +0200 |
| commit | 716b432346b4ffcc3041b6372c7a881ddfef1e11 (patch) | |
| tree | d85b8aa3a81907ba0775f0cc3cb3ba5ed4f230f9 /board | |
| parent | a288018b6ff0adb46e5af79cfa5b9c1a85f10aa5 (diff) | |
| download | barebox-716b432346b4ffcc3041b6372c7a881ddfef1e11.tar.gz barebox-716b432346b4ffcc3041b6372c7a881ddfef1e11.tar.xz | |
pcm038: arbitrary changes to make boot more robust
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'board')
| -rw-r--r-- | board/pcm038/pcm038.c | 34 |
1 files changed, 18 insertions, 16 deletions
diff --git a/board/pcm038/pcm038.c b/board/pcm038/pcm038.c index 53478ea8db..a5d16188bb 100644 --- a/board/pcm038/pcm038.c +++ b/board/pcm038/pcm038.c @@ -276,6 +276,22 @@ static int pll_init(void) { int i = 0; +#define CSCR_VAL CSCR_USB_DIV(3) | \ + CSCR_SD_CNT(3) | \ + CSCR_MSHC_SEL | \ + CSCR_H264_SEL | \ + CSCR_SSI1_SEL | \ + CSCR_SSI2_SEL | \ + CSCR_MCU_SEL | \ + CSCR_SP_SEL | \ + CSCR_ARM_SRC_MPLL | \ + CSCR_ARM_DIV(0) | \ + CSCR_FPM_EN | \ + CSCR_SPEN | \ + CSCR_MPEN + + CSCR = CSCR_VAL | CSCR_AHB_DIV(3); + /* * pll clock initialization - see section 3.4.3 of the i.MX27 manual */ @@ -284,7 +300,7 @@ static int pll_init(void) PLL_PCTL_MFI(7) | PLL_PCTL_MFN(35); /* MPLL = 2 * 26 * 3.83654 MHz = 199.5 MHz */ - SPCTL0 = PLL_PCTL_PD(1) | + SPCTL0 = PLL_PCTL_PD(2) | PLL_PCTL_MFD(12) | PLL_PCTL_MFI(9) | PLL_PCTL_MFN(3); /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */ @@ -294,22 +310,8 @@ static int pll_init(void) * AHB clock = (399 MHz / 3) / (AHB divider = 2) = 66.5 MHz * System clock (HCLK) = 133 MHz */ -#define CSCR_VAL CSCR_USB_DIV(3) | \ - CSCR_SD_CNT(3) | \ - CSCR_MSHC_SEL | \ - CSCR_H264_SEL | \ - CSCR_SSI1_SEL | \ - CSCR_SSI2_SEL | \ - CSCR_MCU_SEL | \ - CSCR_SP_SEL | \ - CSCR_ARM_SRC_MPLL | \ - CSCR_AHB_DIV(1) | \ - CSCR_ARM_DIV(0) | \ - CSCR_FPM_EN | \ - CSCR_SPEN | \ - CSCR_MPEN - CSCR = CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART; + CSCR = CSCR_VAL | CSCR_AHB_DIV(1) | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART; while (i++ < 1000) { while (CCSR & CCSR_32K_SR); |