Merge branch 'for-sha' of git://git.pengutronix.de/git/mkl/u-boot-v2

11 files changed, 656 insertions, 0 deletions

diff --git a/board/mmccpu/Makefile b/board/mmccpu/Makefile
new file mode 100644
index 0000000000..73ef72e210
--- /dev/null
+++ b/board/mmccpu/Makefile
@@ -0,0 +1,2 @@
+obj-y += lowlevel_init.o
+obj-y += init.o
diff --git a/board/mmccpu/config.h b/board/mmccpu/config.h
new file mode 100644
index 0000000000..2ff30205c5
--- /dev/null
+++ b/board/mmccpu/config.h
@@ -0,0 +1,6 @@
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define AT91_MASTER_CLOCK	99532800		/* peripheral = main / 2 */
+
+#endif	/* __CONFIG_H */
diff --git a/board/mmccpu/env/bin/_update b/board/mmccpu/env/bin/_update
new file mode 100644
index 0000000000..fb7cbe8619
--- /dev/null
+++ b/board/mmccpu/env/bin/_update
@@ -0,0 +1,36 @@
+#!/bin/sh
+
+if [ -z "$part" -o -z "$image" ]; then
+	echo "define \$part and \$image"
+	exit 1
+fi
+
+if [ \! -e "$part" ]; then
+	echo "Partition $part does not exist"
+	exit 1
+fi
+
+if [ $# = 1 ]; then
+	image=$1
+fi
+
+if [ x$ip = xdhcp ]; then
+	dhcp
+fi
+
+ping $eth0.serverip
+if [ $? -ne 0 ] ; then
+	echo "update aborted"
+	exit 1
+fi
+
+unprotect $part
+
+echo
+echo "erasing partition $part"
+erase $part
+
+echo
+echo "flashing $image to $part"
+echo
+tftp $image $part
diff --git a/board/mmccpu/env/bin/boot b/board/mmccpu/env/bin/boot
new file mode 100644
index 0000000000..533dea7618
--- /dev/null
+++ b/board/mmccpu/env/bin/boot
@@ -0,0 +1,47 @@
+#!/bin/sh
+
+. /env/config
+
+if [ x$1 = xnand ]; then
+	root=nand
+	kernel=nand
+fi
+
+if [ x$1 = xnet ]; then
+	root=net
+	kernel=net
+fi
+
+if [ x$1 = xnor ]; then
+	root=nor
+	kernel=nor
+fi
+
+if [ x$ip = xdhcp ]; then
+	bootargs="$bootargs ip=dhcp"
+else
+	bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
+fi
+
+if [ x$root = xnand ]; then
+	bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2"
+elif [ x$root = xnor ]; then
+	bootargs="$bootargs root=$rootpart_nor rootfstype=jffs2"
+else
+	bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp"
+fi
+
+bootargs="$bootargs mtdparts=physmap-flash.0:$nor_parts"
+
+if [ $kernel = net ]; then
+	if [ x$ip = xdhcp ]; then
+		dhcp
+	fi
+	tftp $uimage uImage || exit 1
+	bootm uImage
+elif [ $kernel = nor ]; then
+	bootm /dev/nor0.kernel
+else
+	bootm /dev/nand0.kernel.bb
+fi
+
diff --git a/board/mmccpu/env/bin/hush_hack b/board/mmccpu/env/bin/hush_hack
new file mode 100644
index 0000000000..5fffa92ecd
--- /dev/null
+++ b/board/mmccpu/env/bin/hush_hack
@@ -0,0 +1 @@
+nand -a /dev/nand0.*
diff --git a/board/mmccpu/env/bin/init b/board/mmccpu/env/bin/init
new file mode 100644
index 0000000000..ac84bd596f
--- /dev/null
+++ b/board/mmccpu/env/bin/init
@@ -0,0 +1,37 @@
+#!/bin/sh
+
+PATH=/env/bin
+export PATH
+
+. /env/config
+if [ -e /dev/nor0 ]; then
+	addpart /dev/nor0 $nor_parts
+fi
+
+if [ -e /dev/nand0 ]; then
+	addpart /dev/nand0 $nand_parts
+
+	# Uh, oh, hush first expands wildcards and then starts executing
+	# commands. What a bug!
+	source /env/bin/hush_hack
+fi
+
+if [ -z $eth0.ethaddr ]; then
+	while [ -z $eth0.ethaddr ]; do
+		readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr
+	done
+	echo -a /env/config "eth0.ethaddr=$eth0.ethaddr"
+fi
+
+echo
+echo -n "Hit any key to stop autoboot: "
+timeout -a $autoboot_timeout
+if [ $? != 0 ]; then
+	echo
+	echo "type update_kernel nor [<imagename>] to update kernel into flash"
+	echo "type update_root nor [<imagename>] to update rootfs into flash"
+	echo
+	exit
+fi
+
+boot
diff --git a/board/mmccpu/env/bin/update_kernel b/board/mmccpu/env/bin/update_kernel
new file mode 100644
index 0000000000..05c822d860
--- /dev/null
+++ b/board/mmccpu/env/bin/update_kernel
@@ -0,0 +1,15 @@
+#!/bin/sh
+
+. /env/config
+
+image=$uimage
+if [ x$1 = xnand ]; then
+	part=/dev/nand0.kernel.bb
+elif [ x$1 = xnor ]; then
+	part=/dev/nor0.kernel
+else
+	echo "usage: $0 nor|nand [imagename]"
+	exit 1
+fi
+
+. /env/bin/_update $2
diff --git a/board/mmccpu/env/bin/update_root b/board/mmccpu/env/bin/update_root
new file mode 100644
index 0000000000..a75137237b
--- /dev/null
+++ b/board/mmccpu/env/bin/update_root
@@ -0,0 +1,16 @@
+#!/bin/sh
+
+. /env/config
+
+image=$jffs2
+if [ x$1 = xnand ]; then
+	part=/dev/nand0.root.bb
+elif [ x$1 = xnor ]; then
+	part=/dev/nor0.root
+else
+	echo "usage: $0 nor|nand [imagename]"
+	exit 1
+fi
+
+. /env/bin/_update $2
+
diff --git a/board/mmccpu/env/config b/board/mmccpu/env/config
new file mode 100644
index 0000000000..de92684484
--- /dev/null
+++ b/board/mmccpu/env/config
@@ -0,0 +1,30 @@
+#!/bin/sh
+
+# can be either 'net', 'nor' or 'nand''
+kernel=nor
+root=nor
+
+uimage=uImage-mmccpu
+jffs2=root-mmccpu.jffs2
+
+autoboot_timeout=3
+
+nfsroot="/home/kschwinne/src/pengutronix/OSELAS.BSP-Bucyrus-Grabowski-trunk/platform-Bucyrus-mmccpu/root"
+
+bootargs="console=ttyS0,115200 mmccpu=p299"
+
+#nor_parts="256k(uboot)ro,128k(ubootenv),1536k(kernel),-(root)"
+nor_parts="256k(uboot)ro,128k(ubootenv),1536k(kernel),10240k(root),10240k(rootbu),-(data)"
+rootpart_nor="/dev/mtdblock3"
+
+#nand_parts="256k(uboot)ro,64k(ubootenv),1536k(kernel),-(root)"
+#rootpart_nand="/dev/mtdblock7"
+
+# use 'dhcp' to do dhcp in uboot and in kernel
+ip=dhcp
+
+# or set your networking parameters here
+#eth0.ipaddr=a.b.c.d
+#eth0.netmask=a.b.c.d
+#eth0.gateway=a.b.c.d
+#eth0.serverip=a.b.c.d
diff --git a/board/mmccpu/init.c b/board/mmccpu/init.c
new file mode 100644
index 0000000000..d8f9a5d79e
--- /dev/null
+++ b/board/mmccpu/init.c
@@ -0,0 +1,137 @@
+/*
+ * Copyright (C) 2007 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <net.h>
+#include <cfi_flash.h>
+#include <init.h>
+#include <environment.h>
+#include <fec.h>
+#include <asm/armlinux.h>
+#include <asm/mach-types.h>
+#include <partition.h>
+#include <fs.h>
+#include <fcntl.h>
+#include <asm/io.h>
+#include <asm/hardware.h>
+#include <nand.h>
+#include <linux/mtd/nand.h>
+#include <asm/arch/ether.h>
+
+static struct device_d sdram_dev = {
+	.name		= "ram",
+	.id		= "ram0",
+
+	.map_base	= 0x20000000,
+	.size		= 128 * 1024 * 1024,
+
+	.type		= DEVICE_TYPE_DRAM,
+};
+
+static struct device_d cfi_dev = {
+	.name		= "cfi_flash",
+	.id		= "nor0",
+
+	.map_base	= 0x10000000,
+	.size		= 0,	/* zero means autodetect size */
+};
+
+static struct at91sam_ether_platform_data macb_pdata = {
+	.flags		= AT91SAM_ETHER_MII | AT91SAM_ETHER_FORCE_LINK,
+	.phy_addr	= 4,
+};
+
+static struct device_d macb_dev = {
+	.name		= "macb",
+	.id		= "eth0",
+	.map_base	= AT91C_BASE_MACB,
+	.size		= 0x1000,
+	.type		= DEVICE_TYPE_ETHER,
+	.platform_data	= &macb_pdata,
+};
+
+static int mmccpu_devices_init(void)
+{
+	u32 pe = AT91C_PC25_ERXDV |
+		AT91C_PC22_ERX2 |
+		AT91C_PC23_ERX3 |
+		AT91C_PC20_ETX2 |
+		AT91C_PC21_ETX3;
+
+	writel(pe, AT91C_BASE_PIOC + PIO_BSR(0));
+	writel(pe, AT91C_BASE_PIOC + PIO_PDR(0));
+
+	pe = AT91C_PE21_ETXCK |
+		AT91C_PE23_ETX0 |
+		AT91C_PE24_ETX1 |
+		AT91C_PE25_ERX0 |
+		AT91C_PE26_ERX1 |
+		AT91C_PE27_ERXER |
+		AT91C_PE28_ETXEN |
+		AT91C_PE29_EMDC |
+		AT91C_PE30_EMDIO;
+
+	writel(pe, AT91C_BASE_PIOE + PIO_ASR(0));
+	writel(pe, AT91C_BASE_PIOE + PIO_PDR(0));
+
+	/* set PB27 to '1', enable 50MHz oscillator */
+	writel(AT91C_PIO_PB27, AT91C_BASE_PIOB + PIO_PER(0));
+	writel(AT91C_PIO_PB27, AT91C_BASE_PIOB + PIO_OER(0));
+	writel(AT91C_PIO_PB27, AT91C_BASE_PIOB + PIO_SODR(0));
+
+	/* set PB4, PB5 to '1', enable 50MHz oscillator */
+	writel(AT91C_PIO_PB4|AT91C_PIO_PB5, AT91C_BASE_PIOB + PIO_PER(0));
+	writel(AT91C_PIO_PB4|AT91C_PIO_PB5, AT91C_BASE_PIOB + PIO_OER(0));
+	writel(AT91C_PIO_PB4|AT91C_PIO_PB5, AT91C_BASE_PIOB + PIO_SODR(0));
+
+	writel(1 << AT91C_ID_EMAC, AT91C_PMC_PCER);
+
+	register_device(&sdram_dev);
+	register_device(&macb_dev);
+	register_device(&cfi_dev);
+
+	dev_add_partition(&cfi_dev, 0x00000, 256 * 1024, PARTITION_FIXED, "self");
+	dev_add_partition(&cfi_dev, 0x40000, 128 * 1024, PARTITION_FIXED, "env");
+
+	armlinux_set_bootparams((void *)0x20000100);
+	armlinux_set_architecture(MACH_TYPE_MMCCPU);
+
+	return 0;
+}
+
+device_initcall(mmccpu_devices_init);
+
+static struct device_d mmccpu_serial_device = {
+	.name		= "atmel_serial",
+	.id		= "cs0",
+	.map_base	= AT91C_BASE_DBGU,
+	.size		= 4096,
+	.type		= DEVICE_TYPE_CONSOLE,
+};
+
+static int mmccpu_console_init(void)
+{
+	writel(AT91C_PC31_DTXD | AT91C_PC30_DRXD, AT91C_PIOC_PDR);
+
+	register_device(&mmccpu_serial_device);
+	return 0;
+}
+
+console_initcall(mmccpu_console_init);
diff --git a/board/mmccpu/lowlevel_init.S b/board/mmccpu/lowlevel_init.S
new file mode 100644
index 0000000000..4706a924e3
--- /dev/null
+++ b/board/mmccpu/lowlevel_init.S
@@ -0,0 +1,329 @@
+/*
+ * Board specific setup info
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/hardware.h>
+
+#define SDRAM 0x20000000			/* address of the SDRAM */
+
+/* values */
+#define MASTER_PLL_MUL		54
+#define MASTER_PLL_DIV		4
+
+/* clocks */
+#define MOR_VAL			0x00002001	/* CKGR_MOR - enable main osc. */
+#define PLLAR_VAL		(0x2000BF00 | ((MASTER_PLL_MUL - 1)<< 16) | MASTER_PLL_DIV)
+#define PLLBR_VAL		0x10483E0E	/* 48.054857 MHz for USB) */
+
+#define MCKR1_VAL		0x00000100	/* slowclock */
+#define MCKR2_VAL		0x00000102	/* PCK/2 = MCK Master Clock from PLLA */
+
+#define WDTC_WDMR_VAL		0x3fff8fff	/* disable watchdog */
+#define PIOD_PDR_VAL1		0xFFFF0000	/* define PDC[31:16] as DATA[31:16] */
+#define PIOD_PPUDR_VAL		0xFFFF0000	/* no pull-up for D[31:16] */
+#define MATRIX_EBI0CSA_VAL	0x0000010A	/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 1.8V memories */
+#define MATRIX_EBI1CSA_VAL	0x00010100	/* EBI1_CSA, 3.3v, no pull-ups */
+
+/* SDRAM */
+#define SDRC_MR_VAL1		0		/* SDRAMC_MR Mode register */
+#define SDRC_TR_VAL1		0x13c		/* SDRAMC_TR - Refresh Timer register */
+#define SDRC_CR_VAL		0xc533827a	/* SDRAMC_CR - Configuration register */
+#define SDRC_MDR_VAL		0		/* Memory Device Register -> SDRAM */
+#define SDRC_MR_VAL2		0x00000002	/* SDRAMC_MR */
+#define SDRAM_VAL1		0		/* SDRAM_BASE */
+#define SDRC_MR_VAL3		4		/* SDRC_MR */
+#define SDRAM_VAL2		0		/* SDRAM_BASE */
+#define SDRAM_VAL3		0		/* SDRAM_BASE */
+#define SDRAM_VAL4		0		/* SDRAM_BASE */
+#define SDRAM_VAL5		0		/* SDRAM_BASE */
+#define SDRAM_VAL6		0		/* SDRAM_BASE */
+#define SDRAM_VAL7		0		/* SDRAM_BASE */
+#define SDRAM_VAL8		0		/* SDRAM_BASE */
+#define SDRAM_VAL9		0		/* SDRAM_BASE */
+#define SDRC_MR_VAL4		3		/* SDRC_MR */
+#define SDRAM_VAL10		0		/* SDRAM_BASE */
+#define SDRC_MR_VAL5		0		/* SDRC_MR */
+#define SDRAM_VAL11		0		/* SDRAM_BASE */
+#define SDRC_TR_VAL2		0x30c		/* SDRAM_TR */
+#define SDRAM_VAL12		0		/* SDRAM_BASE */
+
+/* setup CS0 (NOR Flash) - 16-bit */
+#if 1
+#define SMC0_SETUP0_VAL		0x00080203	/* SMC_SETUP */
+#define SMC0_PULSE0_VAL		0x0d050705	/* SMC_PULSE */
+#define SMC0_CYCLE0_VAL		0x00100010	/* SMC_CYCLE */
+#define SMC0_CTRL0_VAL		0x00161003	/* SMC_MODE */
+#elif 0	/* slow setup */
+#define SMC0_SETUP0_VAL		0x00080203	/* SMC_SETUP */
+#define SMC0_PULSE0_VAL		0x0d050705	/* SMC_PULSE */
+#define SMC0_CYCLE0_VAL		0x0d000d00	/* SMC_CYCLE */
+#define SMC0_CTRL0_VAL		0x00111003	/* SMC_MODE */
+#else	/* RONETIX' original values */
+#define SMC0_SETUP0_VAL		0x0A0A0A0A	/* SMC_SETUP */
+#define SMC0_PULSE0_VAL		0x0B0B0B0B	/* SMC_PULSE */
+#define SMC0_CYCLE0_VAL		0x00160016	/* SMC_CYCLE */
+#define SMC0_CTRL0_VAL		0x00161003	/* SMC_MODE */
+#endif
+
+
+#define RSTC_RMR_VAL		0xA5000301	/* user reset enable */
+
+
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+.globl board_init_lowlevel
+board_init_lowlevel:
+
+	mov	r5, pc		// r5 = POS1 + 4 current
+POS1:
+	ldr	r0, =POS1	// r0 = POS1 compile
+	ldr	r2, _TEXT_BASE
+	sub	r0, r0, r2	// r0 = POS1-_TEXT_BASE (POS1 relative)
+	sub	r5, r5, r0	// r0 = TEXT_BASE-1
+	sub	r5, r5, #4	// r1 = text base - current
+
+	/* memory control configuration 1 */
+	ldr	r0, =SMRDATA
+	ldr	r2, =SMRDATA1
+	ldr	r1, _TEXT_BASE
+	sub	r0, r0, r1
+	sub	r2, r2, r1
+	add	r0, r0, r5
+	add	r2, r2, r5
+0:
+	/* the address */
+	ldr	r1, [r0], #4
+	/* the value */
+	ldr	r3, [r0], #4
+	str	r3, [r1]
+	cmp	r2, r0
+	bne	0b
+
+/*-----------------------------------------------------------------------------
+;PMC Init Step 1.
+;------------------------------------------------------------------------------
+;- Enable the Main Oscillator
+;----------------------------------------------------------------------------*/
+	/* Test if main oscillator is enabled */
+	ldr 	r0,=AT91C_PMC_SR
+	ldr 	r1, [r0]
+	ldr 	r2,=AT91C_PMC_MOSCS
+	ands 	r1, r1, r2
+
+	ldr	r1, =AT91C_CKGR_MOR
+
+	/* Main oscillator Enable register PMC_MOR: */
+	/* Enable main oscillator, OSCOUNT = 0xFF */
+	ldr 	r0, =0x0000FF01
+	str	r0, [r1]
+
+	/* Reading the PMC Status register to detect when the */
+	/* Main Oscillator is enabled */
+	mov	r4, #AT91C_PMC_MOSCS
+	ldr	r0,=AT91C_PMC_SR
+MOSCS_Loop:
+	ldr	r3, [r0]
+	and	r3, r4, r3
+	cmp	r3, #AT91C_PMC_MOSCS
+	bne	MOSCS_Loop
+
+
+/*-----------------------------------------------------------------------------
+;PMC Init Step 2.
+;------------------------------------------------------------------------------
+;- Setup PLLA
+;----------------------------------------------------------------------------*/
+	ldr	r1, =AT91C_CKGR_PLLAR
+	/* (18.432 MHz / 1) * 13 = 239 MHz */
+	ldr 	r0, =PLLAR_VAL
+	str	r0, [r1]
+
+	/* Reading the PMC Status register to detect */
+	/* when the PLLA is locked */
+	mov	r4, #AT91C_PMC_LOCKA
+	ldr	r0,=AT91C_PMC_SR
+MOSCS_Loop1:
+	ldr	r3, [r0]
+	and	r3, r4, r3
+	cmp	r3, #AT91C_PMC_LOCKA
+	bne	MOSCS_Loop1
+
+
+/*-----------------------------------------------------------------------------
+;PMC Init Step 3.
+;------------------------------------------------------------------------------
+;- Switch on the Main Oscillator 18.432 MHz
+;----------------------------------------------------------------------------*/
+Init_MCKR:
+
+	/* -Master Clock Controller register PMC_MCKR */
+	ldr	r0, =MCKR1_VAL
+	ldr	r1, =AT91C_PMC_MCKR
+	str	r0, [r1]
+
+	/* Reading the PMC Status register to detect */
+	/* when the Master clock is ready */
+	mov	r4, #AT91C_PMC_MCKRDY
+MCKRDY_Loop:
+	ldr	r1, =AT91C_PMC_SR
+	ldr	r3, [r1]
+	and	r3, r4, r3
+	cmp	r3, #AT91C_PMC_MCKRDY
+	bne	MCKRDY_Loop
+
+	ldr	r0, =MCKR2_VAL
+	ldr	r1, =AT91C_PMC_MCKR
+	str	r0, [r1]
+
+	/* Reading the PMC Status register to detect */
+	/* when the Master clock is ready */
+	mov	r4, #AT91C_PMC_MCKRDY
+MCKRDY_Loop1:
+	ldr	r1, =AT91C_PMC_SR
+	ldr	r3, [r1]
+	and	r3, r4, r3
+	cmp	r3, #AT91C_PMC_MCKRDY
+	bne	MCKRDY_Loop1
+
+/*-----------------------------------------------------------------------------
+;PMC Init Step 4.
+;------------------------------------------------------------------------------
+;- Setup PLLB
+;----------------------------------------------------------------------------*/
+	ldr	r1, = AT91C_PMC_PLLBR
+
+	/* 48.054857 MHz = 18432000 * 72 / 14 / 2 for USB) */
+	ldr 	r0, =PLLBR_VAL
+	str	r0, [r1]
+
+	/* Reading the PMC Status register to detect */
+	/* when the PLLB is locked */
+	mov	r4, #AT91C_PMC_LOCKB
+MOSCS_Loop2:
+	ldr	r1, = AT91C_PMC_SR
+	ldr	r3, [r1]
+	and	r3, r4, r3
+	cmp	r3, #AT91C_PMC_LOCKB
+	bne	MOSCS_Loop2
+
+	/* memory control configuration 2 */
+	ldr	r0, =SMRDATA1
+	ldr	r2, =SMRDATA2
+	ldr	r1, _TEXT_BASE
+	sub	r0, r0, r1
+	sub	r2, r2, r1
+	add	r0, r0, r5
+	add	r2, r2, r5
+
+2:
+	/* the address */
+	ldr	r1, [r0], #4
+	/* the value */
+	ldr	r3, [r0], #4
+	str	r3, [r1]
+	cmp	r2, r0
+	bne	2b
+
+	/* everything is fine now */
+	mov	pc, lr
+
+	.ltorg
+
+SMRDATA:
+	.word AT91C_WDTC_WDMR
+	.word WDTC_WDMR_VAL
+	.word AT91C_PIOD_PDR
+	.word PIOD_PDR_VAL1
+	.word AT91C_PIOD_PPUDR
+	.word PIOD_PPUDR_VAL
+	.word AT91C_PIOD_ASR
+	.word PIOD_PPUDR_VAL
+
+	.word AT91C_CCFG_EBI0CSA
+	.word MATRIX_EBI0CSA_VAL
+	.word AT91C_CCFG_EBI1CSA
+	.word MATRIX_EBI1CSA_VAL
+
+	/* flash */
+	.word AT91C_SMC0_CTRL0
+	.word SMC0_CTRL0_VAL
+
+	.word AT91C_SMC0_CYCLE0
+	.word SMC0_CYCLE0_VAL
+
+	.word AT91C_SMC0_PULSE0
+	.word SMC0_PULSE0_VAL
+
+	.word AT91C_SMC0_SETUP0
+	.word SMC0_SETUP0_VAL
+
+SMRDATA1:
+
+	.word AT91C_SDRAMC0_MR
+	.word SDRC_MR_VAL1
+	.word AT91C_SDRAMC0_TR
+	.word SDRC_TR_VAL1
+	.word AT91C_SDRAMC0_CR
+	.word SDRC_CR_VAL
+	.word AT91C_SDRAMC0_MDR
+	.word SDRC_MDR_VAL
+	.word AT91C_SDRAMC0_MR
+	.word SDRC_MR_VAL2
+	.word SDRAM
+	.word SDRAM_VAL1
+	.word AT91C_SDRAMC0_MR
+	.word SDRC_MR_VAL3
+	.word SDRAM
+	.word SDRAM_VAL2
+	.word SDRAM
+	.word SDRAM_VAL3
+	.word SDRAM
+	.word SDRAM_VAL4
+	.word SDRAM
+	.word SDRAM_VAL5
+	.word SDRAM
+	.word SDRAM_VAL6
+	.word SDRAM
+	.word SDRAM_VAL7
+	.word SDRAM
+	.word SDRAM_VAL8
+	.word SDRAM
+	.word SDRAM_VAL9
+	.word AT91C_SDRAMC0_MR
+	.word SDRC_MR_VAL4
+	.word SDRAM
+	.word SDRAM_VAL10
+	.word AT91C_SDRAMC0_MR
+	.word SDRC_MR_VAL5
+	.word SDRAM
+	.word SDRAM_VAL11
+	.word AT91C_SDRAMC0_TR
+	.word SDRC_TR_VAL2
+	.word SDRAM
+	.word SDRAM_VAL12
+	/* User reset enable */
+	.word AT91C_RSTC_RMR
+	.word RSTC_RMR_VAL
+	/* MATRIX_MCFG - REMAP all masters */
+
+SMRDATA2:
+	.word 0