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author | Sascha Hauer <s.hauer@pengutronix.de> | 2008-09-09 14:13:59 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2008-09-09 14:13:59 +0200 |
commit | a288018b6ff0adb46e5af79cfa5b9c1a85f10aa5 (patch) | |
tree | 1550d2a80582f7f8bb4ae9fa44ca9e1f39b60e5d /board | |
parent | 2c02a3914f722036f6be1008a990b7f2daab2f01 (diff) | |
download | barebox-a288018b6ff0adb46e5af79cfa5b9c1a85f10aa5.tar.gz barebox-a288018b6ff0adb46e5af79cfa5b9c1a85f10aa5.tar.xz |
pcm038: implement better waiting for PLLs
Instead of using a trivial counting loop we poll the 32KHz oscillator
to wait for the PLLs to stabilize
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'board')
-rw-r--r-- | board/pcm038/pcm038.c | 36 |
1 files changed, 10 insertions, 26 deletions
diff --git a/board/pcm038/pcm038.c b/board/pcm038/pcm038.c index e800a4a606..53478ea8db 100644 --- a/board/pcm038/pcm038.c +++ b/board/pcm038/pcm038.c @@ -229,7 +229,7 @@ console_initcall(pcm038_console_init); static int pcm038_power_init(void) { #ifdef CONFIG_DRIVER_SPI_MC13783 - volatile int i = 0; + int i = 0; int ret; ret = pmic_power(); @@ -243,26 +243,10 @@ static int pcm038_power_init(void) CSCR |= CSCR_MPLL_RESTART; - /* We need a delay here. We can't use udelay because - * the PLL is not running. Do not remove the volatile - * above because otherwise the compiler will optimize the loop - * away. - */ - while(i++ < 10000); - - CSCR = CSCR_USB_DIV(3) | \ - CSCR_SD_CNT(3) | \ - CSCR_MSHC_SEL | \ - CSCR_H264_SEL | \ - CSCR_SSI1_SEL | \ - CSCR_SSI2_SEL | \ - CSCR_MCU_SEL | \ - CSCR_SP_SEL | \ - CSCR_ARM_SRC_MPLL | \ - CSCR_ARM_DIV(0) | \ - CSCR_AHB_DIV(1) | \ - CSCR_FPM_EN | \ - CSCR_MPEN; + while (i++ < 1000) { + while (CCSR & CCSR_32K_SR); + while (!(CCSR & CCSR_32K_SR)); + } PCDR1 = 0x09030911; @@ -290,9 +274,7 @@ void __bare_init nand_boot(void) static int pll_init(void) { - volatile int i = 0; - - CSCR &= ~0x3; + int i = 0; /* * pll clock initialization - see section 3.4.3 of the i.MX27 manual @@ -329,8 +311,10 @@ static int pll_init(void) CSCR = CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART; - /* add some delay here */ - while(i++ < 0x8000); + while (i++ < 1000) { + while (CCSR & CCSR_32K_SR); + while (!(CCSR & CCSR_32K_SR)); + } /* clock gating enable */ GPCR = 0x00050f08; |