pcm038 startup: Use bit defines rather than hardcoded values in initialisation

1 files changed, 49 insertions, 89 deletions

diff --git a/board/pcm038/lowlevel_init.S b/board/pcm038/lowlevel_init.S
index e603b6c238..0ca2ee8130 100644
--- a/board/pcm038/lowlevel_init.S
+++ b/board/pcm038/lowlevel_init.S
@@ -12,103 +12,43 @@
 	ldr		r1,	=val;	\
 	str		r1,   [r0];
 
-#define CRM_PLL_PCTL_PARAM(pd, fd, fi, fn)  (((pd-1)<<26) + ((fd-1)<<16) + (fi<<10) + (fn<<0))
 
-.macro sdram_init_sha
+#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10)
+
+.macro sdram_init
 	/*
 	 * DDR on CSD0
 	 */
-	writel(0x00000008, 0xD8001010)
-	writel(0x55555555, 0x10027828)
-	writel(0x55555555, 0x10027830)
-	writel(0x55555555, 0x10027834)
-	writel(0x00005005, 0x10027838)
-	writel(0x15555555, 0x1002783C)
-	writel(0x00000004, 0xD8001010)
-	writel(0x006ac73a, 0xD8001004)
-	writel(0x92100000, 0xD8001000)
-	writel(0x00000000, 0xA0000F00)
-	writel(0xA2100000, 0xD8001000)
-	writel(0x00000000, 0xA0000F00)
+	writel(0x00000008, ESDMISC) /* Enable DDR SDRAM operation */
+
+	writel(0x55555555, DSCR(3)) /* Set the driving strength   */
+	writel(0x55555555, DSCR(5))
+	writel(0x55555555, DSCR(6))
+	writel(0x00005005, DSCR(7))
+	writel(0x15555555, DSCR(8))
+
+	writel(0x00000004, ESDMISC) /* Initial reset */
+	writel(0x006ac73a, ESDCFG0)
+
+	writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, ESDCTL0) /* precharge CSD0 all banks */
+	writel(0x00000000, 0xA0000F00)	/* CSD0 precharge address (A10 = 1) */
+	writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0)
+	writel(0x00000000, 0xA0000F00)	/* run auto-refresh cycle to array 0 */
 	writel(0x00000000, 0xA0000F00)
 	writel(0x00000000, 0xA0000F00)
 	writel(0x00000000, 0xA0000F00)
-	writel(0xA2200000, 0xD8001000)
 	writel(0x00000000, 0xA0000F00)
 	writel(0x00000000, 0xA0000F00)
 	writel(0x00000000, 0xA0000F00)
 	writel(0x00000000, 0xA0000F00)
-	writel(0xb2100000, 0xD8001000)
-	ldr		r0, =0xA0000033
-	mov		r1, #0xda
-	strb		r1, [r0]
-	ldr		r0, =0xA1000000
-	mov		r1, #0xff
-	strb		r1, [r0]
-	writel(0x82226080, 0xD8001000)
-.endm
-
-.macro sdram_init_mx27_manual
-	/*
-	 * sdram init sequence, as defined in 18.5.4 of the i.MX27 reference manual
-	 */
-1:
-	ldr r2, =ESD_ESDCTL0		/* base address of registers */
-	ldr r3, =PRE_ALL_CMD		/* SMODE=001 */
-	str r3,(r2,#0x0)		/* put CSD0 in precharge command mode */
-	ldr r4, =SDRAM_CSD0		/* CSD0 precharge address (A10=1) */
-	str r1,(r4,#0x0)		/* precharge CSD0 all banks */
-	ldr r3, =AUTO_REF_CMD		/* SMODE=010 */
-	str r3,(r2,#0x0)		/* put array 0 in auto-refresh mode */
-	ldr r4, =SDRAM_CSD0_BASE	/* CSD0 base address */
-	ldr r6,=0x7			/* load loop counter */
-1:	ldr r5,(r4,#0x0)		/* run auto-refresh cycle to array 0 */
-	subs r6,r6,#1			/* decrease counter value */
-	bne 1b
-	ldr r3, =SET_MODE_REG_CMD	/* SMODE=011 */
-	str r3,(r2,#0x0)		/* setup CSD0 for mode register write */
-	ldr r3, =MODE_REG_VAL0		/* array 0 mode register value */
-	ldrb r5,(r3,#0x0)		/* New mode register value on address bus */
-	ldr r3, =NORMAL_MODE		/* SMODE=000 */
-	str r3,(r2,#0x0)		/* setup CSD0 for normal operation */
-
-ESD_ESDCTL0		.long 0xD8001000 // system/external device dependent data
-SDRAM_CSD0		.long 0x00000000 // system/external device dependent data
-SDRAM_CSD0_BASE		.long 0x00000000 // system/external device dependent data
-PRE_ALL_CMD		.long 0x00000000 // system/external device dependent data (SMODE=001)
-AUTO_REF_CMD		.long 0x00000000 // system/external device dependent data (SMODE=010)
-SET_MODE_REG_CMD	.long 0x00000000 // system/external device dependent data (SMODE=011)
-MODE_REG_VAL0		.long 0x00000000 // system/external device dependent data
-NORMAL_MODE		.long 0x00000000 // system/external device dependent data (SMODE=000)
-.endm
-
-.macro sdram_init_uboot
-	/* configure 16 bit nor flash on cs0 */
-	writel(0x0000CC03, 0xd8002000)
-	writel(0xa0330D01, 0xd8002004)
-	writel(0x00220800, 0xd8002008)
-
-	/* ddr on csd0 - initial reset */
-	writel(0x00000008, 0xD8001010)
-
-	/* configure ddr on csd0 - wait 5000 cycles */
-	writel(0x00000004, 0xD8001010)
-	writel(0x006ac73a, 0xD8001004)
-	writel(0x92100000, 0xD8001000)
-	writel(0x12344321, 0xA0000f00)
-	writel(0xa2100000, 0xD8001000)
-	writel(0x12344321, 0xA0000000)
-	writel(0x12344321, 0xA0000000)
-	writel(0xb2100000, 0xD8001000)
+	writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0)
 	ldr		r0, =0xA0000033
 	mov		r1, #0xda
 	strb		r1, [r0]
 	ldr		r0, =0xA1000000
 	mov		r1, #0xff
 	strb		r1, [r0]
-	writel(0x82226080, 0xD8001000)
-	writel(0xDEADBEEF, 0xA0000000)
-	writel(0x0000000c, 0xD8001010)
+	writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, ESDCTL0)
 .endm
 
 .globl board_init_lowlevel
@@ -130,23 +70,43 @@ board_init_lowlevel:
 
 	/*
 	 * pll clock initialization - see section 3.4.3 of the i.MX27 manual
-	 *
-	 * FIXME: Using the 399*2 MHz values from table 3-8 doens't work
-	 *        with 1.2 V core voltage! Find out if this is
-	 *        documented somewhere.
 	 */
-	writel(0x04331C23, MPCTL0)	/* MPLL = 199.5*2 MHz               */
-	writel(0x040C2403, SPCTL0)	/* SPLL = FIXME (needs review)      */
+	writel(PLL_PCTL_PD(1) |		\
+		PLL_PCTL_MFD(51) |	\
+		PLL_PCTL_MFI(7) |	\
+		PLL_PCTL_MFN(35),	\
+		MPCTL0)	              /* MPLL = 2 * 26 * 3.83654 MHz = 199.5 MHz */
+
+	writel(PLL_PCTL_PD(1) |		\
+		PLL_PCTL_MFD(12) |	\
+		PLL_PCTL_MFI(9) |	\
+		PLL_PCTL_MFN(3),	\
+		SPCTL0)	              /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */
 
 	/*
 	 * ARM clock = (399 MHz / 2) / (ARM divider = 1) = 200 MHz
 	 * AHB clock = (399 MHz / 3) / (AHB divider = 2) = 66.5 MHz
 	 * System clock (HCLK) = 133 MHz
 	 */
-	writel(0x33f38107 | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART, CSCR)
+#define CSCR_VAL CSCR_USB_DIV(3) |	\
+		 CSCR_SD_CNT(3) |	\
+		 CSCR_MSHC_SEL |	\
+		 CSCR_H264_SEL |	\
+		 CSCR_SSI1_SEL |	\
+		 CSCR_SSI2_SEL |	\
+		 CSCR_MCU_SEL |		\
+		 CSCR_SP_SEL |		\
+		 CSCR_ARM_SRC_MPLL |	\
+		 CSCR_AHB_DIV(1) |	\
+		 CSCR_ARM_DIV(0) |	\
+		 CSCR_FPM_EN |		\
+		 CSCR_SPEN |		\
+		 CSCR_MPEN
+
+	writel(CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART, CSCR)
 
 	/* add some delay here */
-	mov r1, #0x1000
+	mov r1, #0x8000
 1:	subs r1, r1, #0x1
 	bne 1b
 
@@ -171,7 +131,7 @@ board_init_lowlevel:
 
 	mov	pc,r10
 1:
-	sdram_init_sha
+	sdram_init
 
 	mov	pc,r10