diff options
author | Juergen Beisert <j.beisert@pengutronix.de> | 2009-06-23 16:31:25 +0200 |
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committer | Juergen Beisert <j.beisert@pengutronix.de> | 2009-07-01 15:58:48 +0200 |
commit | 27acfbda771742c6fdd3a4d044fb45f0a66bb2be (patch) | |
tree | 380584ea44fe9ad93510e7c4cbb4f6d83e196b6b /board | |
parent | bf9679991a8af00adbb2107c727423e571ea5590 (diff) | |
download | barebox-27acfbda771742c6fdd3a4d044fb45f0a66bb2be.tar.gz barebox-27acfbda771742c6fdd3a4d044fb45f0a66bb2be.tar.xz |
Add the basic support for the DIGI a9m2410 CPU card.
Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de>
Diffstat (limited to 'board')
-rw-r--r-- | board/a9m2410/Makefile | 3 | ||||
-rw-r--r-- | board/a9m2410/a9m2410.c | 276 | ||||
-rw-r--r-- | board/a9m2410/config.h | 122 | ||||
-rw-r--r-- | board/a9m2410/env/bin/_update | 36 | ||||
-rw-r--r-- | board/a9m2410/env/bin/boot | 38 | ||||
-rw-r--r-- | board/a9m2410/env/bin/hush_hack | 1 | ||||
-rw-r--r-- | board/a9m2410/env/bin/init | 34 | ||||
-rw-r--r-- | board/a9m2410/env/bin/update_kernel | 13 | ||||
-rw-r--r-- | board/a9m2410/env/bin/update_root | 11 | ||||
-rw-r--r-- | board/a9m2410/env/config | 26 | ||||
-rw-r--r-- | board/a9m2410/lowlevel_init.S | 37 |
11 files changed, 597 insertions, 0 deletions
diff --git a/board/a9m2410/Makefile b/board/a9m2410/Makefile new file mode 100644 index 0000000000..63026f08b2 --- /dev/null +++ b/board/a9m2410/Makefile @@ -0,0 +1,3 @@ + +obj-y += lowlevel_init.o +obj-y += a9m2410.o diff --git a/board/a9m2410/a9m2410.c b/board/a9m2410/a9m2410.c new file mode 100644 index 0000000000..696fc7dbf0 --- /dev/null +++ b/board/a9m2410/a9m2410.c @@ -0,0 +1,276 @@ +/* + * Copyright (C) 2009 Juergen Beisert, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/** + * @file + * @brief a9m2410 Specific Board Initialization routines + * + */ + +#include <common.h> +#include <driver.h> +#include <init.h> +#include <asm/armlinux.h> +#include <asm/mach-types.h> +#include <partition.h> +#include <nand.h> +#include <asm/io.h> +#include <asm/arch/s3c24x0-iomap.h> +#include <asm/arch/s3c24x0-nand.h> + +static struct device_d sdram_dev = { + .name = "ram", + .id = "ram0", + + .map_base = CS6_BASE, + .type = DEVICE_TYPE_DRAM, +}; + +// {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0}, +static struct s3c24x0_nand_platform_data nand_info = { + .nand_timing = CALC_NFCONF_TIMING(A9M2410_TACLS, A9M2410_TWRPH0, A9M2410_TWRPH1) +}; + +static struct device_d nand_dev = { + .name = "s3c24x0_nand", + .map_base = S3C24X0_NAND_BASE, + .platform_data = &nand_info, +}; + +/* + * SMSC 91C111 network controller on the baseboard + * connected to CS line 1 and interrupt line + * GPIO3, data width is 32 bit + */ +static struct device_d network_dev = { + .name = "smc91c111", + .id = "eth0", + .map_base = CS1_BASE + 0x300, + .size = 16, + .type = DEVICE_TYPE_ETHER, +}; + +#if 0 +/* + * dual 16550 based UART on the baseboard + * connected to CS line 2 and interrupt line + * GPIOX (EINT2 and EINT3), data width is 8 bit + */ +static struct device_d ext_serial_dev[] = { + { + .name = "16550", + .id = "serial", + .map_base = CS2_BASE + 0x02000000, /* A25 = 1 */ + .size = 7, + .type = DEVICE_TYPE_CONSOLE, + }, + { + .name = "16550", + .id = "serial", + .map_base = CS2_BASE + 0x04000000, /* A26 = 1 */ + .size = 16, + .type = DEVICE_TYPE_CONSOLE, + } +}; +#endif + +static int a9m2410_devices_init(void) +{ + uint32_t reg; + struct device_d *nand, *dev; + + /* + * detect the current memory size + * Note: On this card the second SDRAM page is not used + */ + reg = readl(BANKSIZE); + + switch (reg &= 0x7) { + case 0: + sdram_dev.size = 32 * 1024 * 1024; + break; + case 1: + sdram_dev.size = 64 * 1024 * 1024; + break; + case 2: + sdram_dev.size = 128 * 1024 * 1024; + break; + case 4: + sdram_dev.size = 2 * 1024 * 1024; + break; + case 5: + sdram_dev.size = 4 * 1024 * 1024; + break; + case 6: + sdram_dev.size = 8 * 1024 * 1024; + break; + case 7: + sdram_dev.size = 16 * 1024 * 1024; + break; + } + + /* ---------- configure the GPIOs ------------- */ + writel(0x007FFFFF, GPACON); + writel(0x00000000, GPCCON); + writel(0x00000000, GPCUP); + writel(0x00000000, GPDCON); + writel(0x00000000, GPDUP); + writel(0xAAAAAAAA, GPECON); + writel(0x0000E03F, GPEUP); + writel(0x00000000, GPBCON); /* all inputs */ + writel(0x00000007, GPBUP); /* pullup disabled for GPB0..3 */ + writel(0x00009000, GPFCON); /* GPF7 CLK_INT#, GPF6 Debug-LED */ + writel(0x000000FF, GPFUP); + writel(readl(GPGDAT) | 0x0010, GPGDAT); /* switch off LCD backlight */ + writel(0xFF00A938, GPGCON); /* switch off USB device */ + writel(0x0000F000, GPGUP); + writel(readl(GPHDAT) | 0x100, GPHDAT); /* switch BOOTINT/GPIO_ON# to high */ + writel(0x000007FF, GPHUP); + writel(0x0029FAAA, GPHCON); + /* + * USB port1 normal, USB port0 normal, USB1 pads for device + * PCLK output on CLKOUT0, UPLL CLK output on CLKOUT1, + * 2nd SDRAM bank off (only bank 1 is used) + */ + writel(0x40140, MISCCR); + + /* ----------- configure the access to the outer space ---------- */ + reg = readl(BWSCON); + + /* CS#1 to access the network controller */ + reg &= ~0xf0; + reg |= 0xe0; + writel(0x1350, BANKCON1); + + /* CS#2 to the dual 16550 UART */ + reg &= ~0xf00; + reg |= 0x400; + writel(0x0d50, BANKCON2); + + writel(reg, BWSCON); + + /* release the reset signal to the network and UART device */ + reg = readl(MISCCR); + reg |= 0x10000; + writel(reg, MISCCR); + + /* ----------- the devices the boot loader should work with -------- */ + register_device(&nand_dev); + register_device(&sdram_dev); + register_device(&network_dev); + +#ifdef CONFIG_NAND + /* ----------- add some vital partitions -------- */ + nand = get_device_by_path("/dev/nand0"); + if (nand) { + dev = dev_add_partition(nand, 0x00000, 0x40000, + PARTITION_FIXED, "self_raw"); + if (dev) { + dev_add_bb_dev(dev, "self0"); + dev = dev_add_partition(nand, 0x40000, 0x20000, + PARTITION_FIXED, "env_raw"); + if (dev) + dev_add_bb_dev(dev, "env0"); + } + } +#endif + armlinux_set_bootparams((void *)sdram_dev.map_base + 0x100); + +/* + * Kernel uses: + * 2.6.29: SMDK2410 = 193 + * 2.6.11: A9M2410 = 697 + */ + armlinux_set_architecture(193/*697*/); /* A9M2410 */ + + return 0; +} + +device_initcall(a9m2410_devices_init); + +#ifdef CONFIG_S3C24XX_NAND_BOOT +void __bare_init nand_boot(void) +{ + s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0, 512); +} +#endif + +static struct device_d a9m2410_serial_device = { + .name = "s3c24x0_serial", + .id = "cs0", + .map_base = UART1_BASE, + .size = UART1_SIZE, + .type = DEVICE_TYPE_CONSOLE, +}; + +static int a9m2410_console_init(void) +{ + register_device(&a9m2410_serial_device); + return 0; +} + +console_initcall(a9m2410_console_init); + +/** @page a9m2410 DIGI's a9m2410 + +This CPU card is based on a Samsung S3C2410 CPU. The card is shipped with: + +- S3C2410\@200 MHz (ARM920T/ARMv4T) +- 12MHz crystal reference +- SDRAM 32 MiB + - Samsung K4M563233E-EE1H + - 2M x 32Bit x 4 Banks Mobile SDRAM + - 90 pin FBGA + - CL3\@133MHz, CL2\@100MHz (CAS/RAS delay 19ns) + - four banks + - 32 bit data bits + - row address size is 11 + - Row cycle time: 69ns + - collumn address size is 9 bits + - Extended temperature range (-25°C...85°C) + - 64ms refresh period (4k) +- NAND Flash 32 MiB + - Samsung KM29U256T + - 32MiB 3,3V 8-bit + - ID: 0xEC, 0x75, 0x??, 0xBD + - 30ns/40ns/20ns +- I2C interface, 100KHz and 400KHz + - Real Time Clock + - Dallas DS1337 + - address 0x68 + - EEPROM + - ST M24LC64 + - address 0x50 + - 16bit addressing +- LCD interface +- Touch Screen interface +- Camera interface +- I2S interface +- AC97 Audio-CODEC interface +- SD card interface +- 3 serial RS232 interfaces +- Host and device USB interface, USB1.1 compliant +- Ethernet interface + - 10Mbps, Cirrus Logic, CS8900A (on the CPU card) or + - 10/100Mbps, SMSC 91C111 (on the baseboard) +- SPI interface +- JTAG interface + +*/ diff --git a/board/a9m2410/config.h b/board/a9m2410/config.h new file mode 100644 index 0000000000..87b05fc55d --- /dev/null +++ b/board/a9m2410/config.h @@ -0,0 +1,122 @@ +/** + * @file + * @brief Global defintions for the ARM S3C2410 based a9m2410 CPU card + */ +/* This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/** + * The external clock reference is a 12.0MHz crystal + */ +#define S3C24XX_CLOCK_REFERENCE 12000000 + +/** + * Define the main clock configuration to be used in register CLKDIVN + * + * We must limit the frequency of the connected SDRAMs with the clock ratio + * setup to 1:2:4. This will result into FCLK:HCLK:PCLK = 200Mhz:100MHz:50MHz + */ +#define BOARD_SPECIFIC_CLKDIVN 0x003 + +/** + * Define the MPLL configuration to be used in register MPLLCON + * + * We want the MPLL to run at 202.80MHz + */ +#define BOARD_SPECIFIC_MPLL ((0xA1 << 12) + (3 << 4) + 1) + +/** + * Define the UPLL configuration to be used in register UPLLCON + * + * We want the UPLL to run at 48.0MHz + */ +#define BOARD_SPECIFIC_UPLL ((0x78 << 12) + (2 << 4) + 3) + +/* + * SDRAM configuration for Samsung K4M563233E + * - 2M x 32Bit x 4 Banks Mobile SDRAM + * - 90 pin FBGA + * - CL2@100MHz + */ +/* + * SDRAM uses 32bit width + */ +#define BOARD_SPECIFIC_BWSCON ((0x02 << 24) + (0x02 << 28)) +/* + * 32MiB SDRAM in bank6 + * - MT = 11 (= sync dram type) + * - Trcd = 00 (= CL2) + * - SCAN = 01 (= 9 bit collumns) + */ +#define BOARD_SPECIFIC_BANKCON6 ((0x3 << 15) + (0x0 << 2) + 0x1) +/* + * No memory in bank7 + */ +#define BOARD_SPECIFIC_BANKCON7 ((0x3 << 15) + (0x0 << 2) + 0x1) +/* + * SDRAM refresh settings + * - REFEN = 1 (= refresh enabled) + * - TREFMD = 0 (= auto refresh) + * - Trp = 00 (= 2 RAS precharge clocks) + * - Tsrc = 01 (= 5 clocks -> row cycle time @100MHz 2+5=7 -> 70ns) + * - Refrsh = 2^11 + 1 - 100 * 15.6 = 2049 - 1560 = 489 + */ +#define BOARD_SPECIFIC_REFRESH ((0x1 << 23) + (0x0 << 22) + (0x0 << 20) + (0x1 << 18) + 489) +/* + * SDRAM banksize + * - BURST_EN = 1 (= burst mode enabled) + * - SCKE_EN = 1 (= SDRAM SCKE enabled) + * - SCLK_EN = 1 (= clock active only during accesses) + * - BK67MAP = 000 (= 32MiB) + */ +#define BOARD_SPECIFIC_BANKSIZE ((1 << 7) + (1 << 5) + (0 << 4) + 0) +/* + * SDRAM mode register bank6 + * CL = 010 (= 2 clocks) + */ +#define BOARD_SPECIFIC_MRSRB6 (0x2 << 4) +/* + * SDRAM mode register bank7 + * CL = 010 (= 2 clocks) + */ +#define BOARD_SPECIFIC_MRSRB7 (0x2 << 4) + +/* + * Flash access timings + * Tacls = 0ns (but 20ns data setup time) + * Twrph0 = 25ns (write) 35ns (read) + * Twrph1 = 10ns (10ns data hold time) + * Read cycle time = 50ns + * + * Assumed HCLK is 100MHz + * Tacls = 1 (-> 20ns) + * Twrph0 = 3 (-> 40ns) + * Twrph1 = 1 (-> 20ns) + * Cycle time = 80ns + */ +#define A9M2410_TACLS 1 +#define A9M2410_TWRPH0 3 +#define A9M2410_TWRPH1 1 + +/* needed in the generic NAND boot code only */ +#ifdef CONFIG_S3C24XX_NAND_BOOT +# define BOARD_DEFAULT_NAND_TIMING CALC_NFCONF_TIMING(A9M2410_TACLS, A9M2410_TWRPH0, A9M2410_TWRPH1) +#endif + +#endif /* __CONFIG_H */ diff --git a/board/a9m2410/env/bin/_update b/board/a9m2410/env/bin/_update new file mode 100644 index 0000000000..fb7cbe8619 --- /dev/null +++ b/board/a9m2410/env/bin/_update @@ -0,0 +1,36 @@ +#!/bin/sh + +if [ -z "$part" -o -z "$image" ]; then + echo "define \$part and \$image" + exit 1 +fi + +if [ \! -e "$part" ]; then + echo "Partition $part does not exist" + exit 1 +fi + +if [ $# = 1 ]; then + image=$1 +fi + +if [ x$ip = xdhcp ]; then + dhcp +fi + +ping $eth0.serverip +if [ $? -ne 0 ] ; then + echo "update aborted" + exit 1 +fi + +unprotect $part + +echo +echo "erasing partition $part" +erase $part + +echo +echo "flashing $image to $part" +echo +tftp $image $part diff --git a/board/a9m2410/env/bin/boot b/board/a9m2410/env/bin/boot new file mode 100644 index 0000000000..59fa60e4e9 --- /dev/null +++ b/board/a9m2410/env/bin/boot @@ -0,0 +1,38 @@ +#!/bin/sh + +. /env/config + +if [ x$1 = xnand ]; then + root=nand + kernel=nand +fi + +if [ x$1 = xnet ]; then + root=net + kernel=net +fi + +if [ x$ip = xdhcp ]; then + bootargs="$bootargs ip=dhcp" +else + bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" +fi + +if [ x$root = xnand ]; then + bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2" +else + bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp" +fi + +bootargs="$bootargs mtdparts=\"NAND 32MiB 3,3V 8-bit:$nand_parts\"" + +if [ x$kernel = xnet ]; then + if [ x$ip = xdhcp ]; then + dhcp + fi + tftp $uimage uImage || exit 1 + bootm uImage +else + bootm /dev/nand0.kernel.bb +fi + diff --git a/board/a9m2410/env/bin/hush_hack b/board/a9m2410/env/bin/hush_hack new file mode 100644 index 0000000000..5fffa92ecd --- /dev/null +++ b/board/a9m2410/env/bin/hush_hack @@ -0,0 +1 @@ +nand -a /dev/nand0.* diff --git a/board/a9m2410/env/bin/init b/board/a9m2410/env/bin/init new file mode 100644 index 0000000000..5ae44dd455 --- /dev/null +++ b/board/a9m2410/env/bin/init @@ -0,0 +1,34 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config + +if [ -e /dev/nand0 ]; then + addpart /dev/nand0 $nand_parts + + # Uh, oh, hush first expands wildcards and then starts executing + # commands. What a bug! + source /env/bin/hush_hack +fi + +if [ -z $eth0.ethaddr ]; then + while [ -z $eth0.ethaddr ]; do + readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr + done + echo -a /env/config "eth0.ethaddr=$eth0.ethaddr" +fi + +echo +echo -n "Hit any key to stop autoboot: " +timeout -a $autoboot_timeout +if [ $? != 0 ]; then + echo + echo "type update_kernel [<imagename>] to update kernel into flash" + echo "type update_root [<imagename>] to update rootfs into flash" + echo + exit +fi + +boot diff --git a/board/a9m2410/env/bin/update_kernel b/board/a9m2410/env/bin/update_kernel new file mode 100644 index 0000000000..c43a55785b --- /dev/null +++ b/board/a9m2410/env/bin/update_kernel @@ -0,0 +1,13 @@ +#!/bin/sh + +. /env/config + +part=/dev/nand0.kernel.bb + +if [ x$1 = x ]; then + image=$uimage +else + image=$1 +fi + +. /env/bin/_update $image diff --git a/board/a9m2410/env/bin/update_root b/board/a9m2410/env/bin/update_root new file mode 100644 index 0000000000..34139e5dce --- /dev/null +++ b/board/a9m2410/env/bin/update_root @@ -0,0 +1,11 @@ +#!/bin/sh + +. /env/config + +if [ x$1 = x ]; then + image=$jffs2 +else + image=$1 +fi + +. /env/bin/_update $image diff --git a/board/a9m2410/env/config b/board/a9m2410/env/config new file mode 100644 index 0000000000..7dbd544e24 --- /dev/null +++ b/board/a9m2410/env/config @@ -0,0 +1,26 @@ +#!/bin/sh + +# can be either 'net' or 'nand'' +kernel=net +root=net + +uimage=uImage-a9m2410 +jffs2=root-a9m2410.jffs2 + +autoboot_timeout=3 + +nfsroot="/nfsexport/OSELAS.BSP-Hesch-TMU-1/platform-FS_A9M2410/root" +bootargs="console=ttySAC0,38400" + +nand_parts="256k(uboot)ro,128k(ubootenv),1536k(kernel),-(root)" +rootpart_nand="/dev/mtdblock3" + +# use 'dhcp' to do dhcp in uboot and in kernel +#ip=dhcp + +# or set your networking parameters here +eth0.ipaddr=192.168.42.31 +eth0.netmask=255.255.0.0 +eth0.gateway=192.168.23.1 +eth0.serverip=192.168.23.2 +eth0.ethaddr=00:04:f3:00:06:35 diff --git a/board/a9m2410/lowlevel_init.S b/board/a9m2410/lowlevel_init.S new file mode 100644 index 0000000000..1af42ddcd1 --- /dev/null +++ b/board/a9m2410/lowlevel_init.S @@ -0,0 +1,37 @@ +/* + * + */ + +#include <config.h> +#include <asm/arch/s3c24x0-iomap.h> + + .section ".text_bare_init.board_init_lowlevel","ax" + +.globl board_init_lowlevel +board_init_lowlevel: + + mov r10, lr /* save the link register */ + + bl s3c24x0_disable_wd + + /* skip everything here if we are already running from SDRAM */ + cmp pc, #S3C24X0_SDRAM_BASE + blo 1f + cmp pc, #S3C24X0_SDRAM_END + bhs 1f + + mov pc, r10 + +/* we are running from NOR or NAND/SRAM memory. Do further initialisation */ +1: + bl s3c24x0_pll_init + + bl s3c24x0_sdram_init + +#ifdef CONFIG_S3C24XX_NAND_BOOT + mov lr, r10 /* restore the link register */ +/* up to here we are running from the internal SRAM area */ + b s3c24x0_nand_boot /* does return directly to our caller into SDRAM */ +#else + mov pc, r10 +#endif |