at91sam9: switch to the same api as the kernel

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

9 files changed, 325 insertions, 730 deletions

diff --git a/board/at91sam9260ek/init.c b/board/at91sam9260ek/init.c
index 2077306d60..d484e9b46c 100644
--- a/board/at91sam9260ek/init.c
+++ b/board/at91sam9260ek/init.c
@@ -34,19 +34,18 @@
 #include <nand.h>
 #include <linux/mtd/nand.h>
 #include <asm/arch/board.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/sam9_smc.h>
 #include <gpio.h>
 
-#define NAND_READY_GPIO (32 * 2 + 13) /* Port C pin 13 */
-#define NAND_ENABLE_GPIO (32 * 2 + 14) /* Port C pin 14 */
-
 static struct atmel_nand_data nand_pdata = {
 	.ale		= 21,
 	.cle		= 22,
 /*	.det_pin	= ... not connected */
-	.ecc_base	= (void __iomem *)AT91C_BASE_HECC,
+	.ecc_base	= (void __iomem *)(AT91_BASE_SYS + AT91_ECC),
 	.ecc_mode	= NAND_ECC_HW,
-	.rdy_pin	= NAND_READY_GPIO,
-	.enable_pin	= NAND_ENABLE_GPIO,
+	.rdy_pin	= AT91_PIN_PC13,
+	.enable_pin	= AT91_PIN_PC14,
 #if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
 	.bus_width_16	= 1,
 #else
@@ -54,6 +53,38 @@ static struct atmel_nand_data nand_pdata = {
 #endif
 };
 
+static struct sam9_smc_config ek_nand_smc_config = {
+	.ncs_read_setup		= 0,
+	.nrd_setup		= 1,
+	.ncs_write_setup	= 0,
+	.nwe_setup		= 1,
+
+	.ncs_read_pulse		= 3,
+	.nrd_pulse		= 3,
+	.ncs_write_pulse	= 3,
+	.nwe_pulse		= 3,
+
+	.read_cycle		= 5,
+	.write_cycle		= 5,
+
+	.mode			= AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
+	.tdf_cycles		= 2,
+};
+
+static void ek_add_device_nand(void)
+{
+	/* setup bus-width (8 or 16) */
+	if (nand_pdata.bus_width_16)
+		ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
+	else
+		ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
+
+	/* configure chip-select 3 (NAND) */
+	sam9_smc_configure(3, &ek_nand_smc_config);
+
+	at91_add_device_nand(&nand_pdata);
+}
+
 static struct at91_ether_platform_data macb_pdata = {
 	.flags    = AT91SAM_ETHER_RMII,
 	.phy_addr = 0,
@@ -61,14 +92,11 @@ static struct at91_ether_platform_data macb_pdata = {
 
 static int at91sam9260ek_devices_init(void)
 {
-	gpio_direction_input(NAND_READY_GPIO);
-	gpio_direction_output(NAND_ENABLE_GPIO, 1);
-
-	at91_add_device_nand(&nand_pdata);
+	ek_add_device_nand();
 	at91_add_device_eth(&macb_pdata);
 
 	at91_add_device_sdram(64 * 1024 * 1024);
-	armlinux_set_bootparams((void *)0x20000100);
+	armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
 	armlinux_set_architecture(MACH_TYPE_AT91SAM9260EK);
 
 	devfs_add_partition("nand0", 0x00000, 0x80000, PARTITION_FIXED, "self_raw");
@@ -83,7 +111,7 @@ device_initcall(at91sam9260ek_devices_init);
 
 static int at91sam9260ek_console_init(void)
 {
-	at91_register_uart(0);
+	at91_register_uart(0, 0);
 	return 0;
 }
 
diff --git a/board/mmccpu/Makefile b/board/mmccpu/Makefile
index 73ef72e210..eb072c0161 100644
--- a/board/mmccpu/Makefile
+++ b/board/mmccpu/Makefile
@@ -1,2 +1 @@
-obj-y += lowlevel_init.o
 obj-y += init.o
diff --git a/board/mmccpu/config.h b/board/mmccpu/config.h
index 2ff30205c5..1133b8f040 100644
--- a/board/mmccpu/config.h
+++ b/board/mmccpu/config.h
@@ -3,4 +3,139 @@
 
 #define AT91_MASTER_CLOCK	99532800		/* peripheral = main / 2 */
 
+/* values */
+#define MASTER_PLL_MUL		54
+#define MASTER_PLL_DIV		4
+
+/* clocks */
+#define CONFIG_SYS_MOR_VAL						\
+		(AT91_PMC_MOSCEN |					\
+		 (255 << 8))		/* Main Oscillator Start-up Time */
+#define CONFIG_SYS_PLLAR_VAL						\
+		(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
+		 AT91_PMC_OUT |						\
+		 AT91_PMC_PLLCOUNT |	/* PLL Counter */		\
+		 (2 << 28) |		/* PLL Clock Frequency Range */	\
+		 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
+
+/* PCK/2 = MCK Master Clock from PLLA */
+#define	CONFIG_SYS_MCKR1_VAL		\
+		(AT91_PMC_CSS_SLOW |	\
+		 AT91_PMC_PRES_1 |	\
+		 AT91SAM9_PMC_MDIV_2 |	\
+		 AT91_PMC_PDIV_1)
+/* PCK/2 = MCK Master Clock from PLLA */
+#define	CONFIG_SYS_MCKR2_VAL		\
+		(AT91_PMC_CSS_PLLA |	\
+		 AT91_PMC_PRES_1 |	\
+		 AT91SAM9_PMC_MDIV_2 |	\
+		 AT91_PMC_PDIV_1)
+
+/* define PDC[31:16] as DATA[31:16] */
+#define CONFIG_SYS_PIOD_PDR_VAL1	0xFFFF0000
+/* no pull-up for D[31:16] */
+#define CONFIG_SYS_PIOD_PPUDR_VAL	0xFFFF0000
+/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 1.8V memories */
+#define CONFIG_SYS_MATRIX_EBI0CSA_VAL					\
+	(AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_1_8V |	\
+	 AT91_MATRIX_EBI0_CS1A_SDRAMC | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA)
+
+/* SDRAM */
+/* SDRAMC_MR Mode register */
+#define CONFIG_SYS_SDRC_MR_VAL1		0
+/* SDRAMC_TR - Refresh Timer register */
+#define CONFIG_SYS_SDRC_TR_VAL1		0x13c
+/* SDRAMC_CR - Configuration register*/
+#define CONFIG_SYS_SDRC_CR_VAL							\
+		(AT91_SDRAMC_NC_9 |						\
+		 AT91_SDRAMC_NR_13 |						\
+		 AT91_SDRAMC_NB_4 |						\
+		 AT91_SDRAMC_CAS_3 |						\
+		 AT91_SDRAMC_DBW_32 |						\
+		 (2 <<  8) |	/* tWR -  Write Recovery Delay */		\
+		 (8 << 12) |	/* tRC -  Row Cycle Delay */			\
+		 (2 << 16) |	/* tRP -  Row Precharge Delay */		\
+		 (2 << 20) |	/* tRCD - Row to Column Delay */		\
+		 (5 << 24) |	/* tRAS - Active to Precharge Delay */		\
+		 (12 << 28))	/* tXSR - Exit Self Refresh to Active Delay */
+
+/* Memory Device Register -> SDRAM */
+#define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
+#define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
+#define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
+#define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
+#define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
+#define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_TR_VAL2		780		/* SDRAM_TR */
+#define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */
+
+/* setup CS0 (NOR Flash) - 16-bit */
+#if 1
+#define CONFIG_SYS_SMC0_SETUP0_VAL					\
+		(AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) |	\
+		 AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0))
+#define CONFIG_SYS_SMC0_PULSE0_VAL					\
+		(AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) |	\
+		 AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13))
+#define CONFIG_SYS_SMC0_CYCLE0_VAL	\
+		(AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16))
+#define CONFIG_SYS_SMC0_MODE0_VAL				\
+		(AT91_SMC_READMODE | AT91_SMC_WRITEMODE |	\
+		 AT91_SMC_DBW_16 |				\
+		 AT91_SMC_TDFMODE |				\
+		 AT91_SMC_TDF_(6))
+#elif 0	/* slow setup */
+#define CONFIG_SYS_SMC0_SETUP0_VAL					\
+		(AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) |	\
+		 AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0))
+#define CONFIG_SYS_SMC0_PULSE0_VAL					\
+		(AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) |	\
+		 AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13))
+#define CONFIG_SYS_SMC0_CYCLE0_VAL	\
+		(AT91_SMC_NWECYCLE_(0xd00) | AT91_SMC_NRDCYCLE_(0xd00))
+#define CONFIG_SYS_SMC0_MODE0_VAL				\
+		(AT91_SMC_READMODE | AT91_SMC_WRITEMODE |	\
+		 AT91_SMC_DBW_16 |				\
+		 AT91_SMC_TDFMODE |				\
+		 AT91_SMC_TDF_(1))
+#else	/* RONETIX' original values */
+#define CONFIG_SYS_SMC0_SETUP0_VAL					\
+		(AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) |	\
+		 AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
+#define CONFIG_SYS_SMC0_PULSE0_VAL					\
+		(AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) |	\
+		 AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
+#define CONFIG_SYS_SMC0_CYCLE0_VAL	\
+		(AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
+#define CONFIG_SYS_SMC0_MODE0_VAL				\
+		(AT91_SMC_READMODE | AT91_SMC_WRITEMODE |	\
+		 AT91_SMC_DBW_16 |				\
+		 AT91_SMC_TDFMODE |				\
+		 AT91_SMC_TDF_(6))
+#endif
+
+/* user reset enable */
+#define CONFIG_SYS_RSTC_RMR_VAL			\
+		(AT91_RSTC_KEY |		\
+		AT91_RSTC_PROCRST |		\
+		AT91_RSTC_RSTTYP_WAKEUP |	\
+		AT91_RSTC_RSTTYP_WATCHDOG)
+
+/* Disable Watchdog */
+#define CONFIG_SYS_WDTC_WDMR_VAL				\
+		(AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |	\
+		 AT91_WDT_WDV |					\
+		 AT91_WDT_WDDIS |				\
+		 AT91_WDT_WDD)
+
 #endif	/* __CONFIG_H */
diff --git a/board/mmccpu/init.c b/board/mmccpu/init.c
index 5ef5020784..7f519e449a 100644
--- a/board/mmccpu/init.c
+++ b/board/mmccpu/init.c
@@ -33,11 +33,14 @@
 #include <asm/hardware.h>
 #include <nand.h>
 #include <linux/mtd/nand.h>
+#include <asm/arch/at91_pmc.h>
 #include <asm/arch/board.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
 
 static struct device_d cfi_dev = {
 	.name		= "cfi_flash",
-	.map_base	= 0x10000000,
+	.map_base	= AT91_CHIPSELECT_0,
 	.size		= 0,	/* zero means autodetect size */
 };
 
@@ -48,39 +51,16 @@ static struct at91_ether_platform_data macb_pdata = {
 
 static int mmccpu_devices_init(void)
 {
-	u32 pe = AT91C_PC25_ERXDV |
-		AT91C_PC22_ERX2 |
-		AT91C_PC23_ERX3 |
-		AT91C_PC20_ETX2 |
-		AT91C_PC21_ETX3;
+	/*
+	 * PB27 enables the 50MHz oscillator for Ethernet PHY
+	 * 1 - enable
+	 * 0 - disable
+	 */
+	at91_set_gpio_output(AT91_PIN_PB27, 1);
+	at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */
 
-	writel(pe, AT91C_BASE_PIOC + PIO_BSR(0));
-	writel(pe, AT91C_BASE_PIOC + PIO_PDR(0));
-
-	pe = AT91C_PE21_ETXCK |
-		AT91C_PE23_ETX0 |
-		AT91C_PE24_ETX1 |
-		AT91C_PE25_ERX0 |
-		AT91C_PE26_ERX1 |
-		AT91C_PE27_ERXER |
-		AT91C_PE28_ETXEN |
-		AT91C_PE29_EMDC |
-		AT91C_PE30_EMDIO;
-
-	writel(pe, AT91C_BASE_PIOE + PIO_ASR(0));
-	writel(pe, AT91C_BASE_PIOE + PIO_PDR(0));
-
-	/* set PB27 to '1', enable 50MHz oscillator */
-	writel(AT91C_PIO_PB27, AT91C_BASE_PIOB + PIO_PER(0));
-	writel(AT91C_PIO_PB27, AT91C_BASE_PIOB + PIO_OER(0));
-	writel(AT91C_PIO_PB27, AT91C_BASE_PIOB + PIO_SODR(0));
-
-	/* set PB4, PB5 to '1', enable 50MHz oscillator */
-	writel(AT91C_PIO_PB4|AT91C_PIO_PB5, AT91C_BASE_PIOB + PIO_PER(0));
-	writel(AT91C_PIO_PB4|AT91C_PIO_PB5, AT91C_BASE_PIOB + PIO_OER(0));
-	writel(AT91C_PIO_PB4|AT91C_PIO_PB5, AT91C_BASE_PIOB + PIO_SODR(0));
-
-	writel(1 << AT91C_ID_EMAC, AT91C_PMC_PCER);
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
 
 	at91_add_device_sdram(128 * 1024 * 1024);
 	at91_add_device_eth(&macb_pdata);
@@ -89,7 +69,7 @@ static int mmccpu_devices_init(void)
 	devfs_add_partition("nor0", 0x00000, 256 * 1024, PARTITION_FIXED, "self0");
 	devfs_add_partition("nor0", 0x40000, 128 * 1024, PARTITION_FIXED, "env0");
 
-	armlinux_set_bootparams((void *)0x20000100);
+	armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
 	armlinux_set_architecture(MACH_TYPE_MMCCPU);
 
 	return 0;
@@ -99,9 +79,7 @@ device_initcall(mmccpu_devices_init);
 
 static int mmccpu_console_init(void)
 {
-	writel(AT91C_PC31_DTXD | AT91C_PC30_DRXD, AT91C_PIOC_PDR);
-
-	at91_register_uart(0);
+	at91_register_uart(0, 0);
 	return 0;
 }
 
diff --git a/board/mmccpu/lowlevel_init.S b/board/mmccpu/lowlevel_init.S
deleted file mode 100644
index 4706a924e3..0000000000
--- a/board/mmccpu/lowlevel_init.S
+++ /dev/null
@@ -1,329 +0,0 @@
-/*
- * Board specific setup info
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm/arch/hardware.h>
-
-#define SDRAM 0x20000000			/* address of the SDRAM */
-
-/* values */
-#define MASTER_PLL_MUL		54
-#define MASTER_PLL_DIV		4
-
-/* clocks */
-#define MOR_VAL			0x00002001	/* CKGR_MOR - enable main osc. */
-#define PLLAR_VAL		(0x2000BF00 | ((MASTER_PLL_MUL - 1)<< 16) | MASTER_PLL_DIV)
-#define PLLBR_VAL		0x10483E0E	/* 48.054857 MHz for USB) */
-
-#define MCKR1_VAL		0x00000100	/* slowclock */
-#define MCKR2_VAL		0x00000102	/* PCK/2 = MCK Master Clock from PLLA */
-
-#define WDTC_WDMR_VAL		0x3fff8fff	/* disable watchdog */
-#define PIOD_PDR_VAL1		0xFFFF0000	/* define PDC[31:16] as DATA[31:16] */
-#define PIOD_PPUDR_VAL		0xFFFF0000	/* no pull-up for D[31:16] */
-#define MATRIX_EBI0CSA_VAL	0x0000010A	/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 1.8V memories */
-#define MATRIX_EBI1CSA_VAL	0x00010100	/* EBI1_CSA, 3.3v, no pull-ups */
-
-/* SDRAM */
-#define SDRC_MR_VAL1		0		/* SDRAMC_MR Mode register */
-#define SDRC_TR_VAL1		0x13c		/* SDRAMC_TR - Refresh Timer register */
-#define SDRC_CR_VAL		0xc533827a	/* SDRAMC_CR - Configuration register */
-#define SDRC_MDR_VAL		0		/* Memory Device Register -> SDRAM */
-#define SDRC_MR_VAL2		0x00000002	/* SDRAMC_MR */
-#define SDRAM_VAL1		0		/* SDRAM_BASE */
-#define SDRC_MR_VAL3		4		/* SDRC_MR */
-#define SDRAM_VAL2		0		/* SDRAM_BASE */
-#define SDRAM_VAL3		0		/* SDRAM_BASE */
-#define SDRAM_VAL4		0		/* SDRAM_BASE */
-#define SDRAM_VAL5		0		/* SDRAM_BASE */
-#define SDRAM_VAL6		0		/* SDRAM_BASE */
-#define SDRAM_VAL7		0		/* SDRAM_BASE */
-#define SDRAM_VAL8		0		/* SDRAM_BASE */
-#define SDRAM_VAL9		0		/* SDRAM_BASE */
-#define SDRC_MR_VAL4		3		/* SDRC_MR */
-#define SDRAM_VAL10		0		/* SDRAM_BASE */
-#define SDRC_MR_VAL5		0		/* SDRC_MR */
-#define SDRAM_VAL11		0		/* SDRAM_BASE */
-#define SDRC_TR_VAL2		0x30c		/* SDRAM_TR */
-#define SDRAM_VAL12		0		/* SDRAM_BASE */
-
-/* setup CS0 (NOR Flash) - 16-bit */
-#if 1
-#define SMC0_SETUP0_VAL		0x00080203	/* SMC_SETUP */
-#define SMC0_PULSE0_VAL		0x0d050705	/* SMC_PULSE */
-#define SMC0_CYCLE0_VAL		0x00100010	/* SMC_CYCLE */
-#define SMC0_CTRL0_VAL		0x00161003	/* SMC_MODE */
-#elif 0	/* slow setup */
-#define SMC0_SETUP0_VAL		0x00080203	/* SMC_SETUP */
-#define SMC0_PULSE0_VAL		0x0d050705	/* SMC_PULSE */
-#define SMC0_CYCLE0_VAL		0x0d000d00	/* SMC_CYCLE */
-#define SMC0_CTRL0_VAL		0x00111003	/* SMC_MODE */
-#else	/* RONETIX' original values */
-#define SMC0_SETUP0_VAL		0x0A0A0A0A	/* SMC_SETUP */
-#define SMC0_PULSE0_VAL		0x0B0B0B0B	/* SMC_PULSE */
-#define SMC0_CYCLE0_VAL		0x00160016	/* SMC_CYCLE */
-#define SMC0_CTRL0_VAL		0x00161003	/* SMC_MODE */
-#endif
-
-
-#define RSTC_RMR_VAL		0xA5000301	/* user reset enable */
-
-
-_TEXT_BASE:
-	.word	TEXT_BASE
-
-.globl board_init_lowlevel
-board_init_lowlevel:
-
-	mov	r5, pc		// r5 = POS1 + 4 current
-POS1:
-	ldr	r0, =POS1	// r0 = POS1 compile
-	ldr	r2, _TEXT_BASE
-	sub	r0, r0, r2	// r0 = POS1-_TEXT_BASE (POS1 relative)
-	sub	r5, r5, r0	// r0 = TEXT_BASE-1
-	sub	r5, r5, #4	// r1 = text base - current
-
-	/* memory control configuration 1 */
-	ldr	r0, =SMRDATA
-	ldr	r2, =SMRDATA1
-	ldr	r1, _TEXT_BASE
-	sub	r0, r0, r1
-	sub	r2, r2, r1
-	add	r0, r0, r5
-	add	r2, r2, r5
-0:
-	/* the address */
-	ldr	r1, [r0], #4
-	/* the value */
-	ldr	r3, [r0], #4
-	str	r3, [r1]
-	cmp	r2, r0
-	bne	0b
-
-/*-----------------------------------------------------------------------------
-;PMC Init Step 1.
-;------------------------------------------------------------------------------
-;- Enable the Main Oscillator
-;----------------------------------------------------------------------------*/
-	/* Test if main oscillator is enabled */
-	ldr 	r0,=AT91C_PMC_SR
-	ldr 	r1, [r0]
-	ldr 	r2,=AT91C_PMC_MOSCS
-	ands 	r1, r1, r2
-
-	ldr	r1, =AT91C_CKGR_MOR
-
-	/* Main oscillator Enable register PMC_MOR: */
-	/* Enable main oscillator, OSCOUNT = 0xFF */
-	ldr 	r0, =0x0000FF01
-	str	r0, [r1]
-
-	/* Reading the PMC Status register to detect when the */
-	/* Main Oscillator is enabled */
-	mov	r4, #AT91C_PMC_MOSCS
-	ldr	r0,=AT91C_PMC_SR
-MOSCS_Loop:
-	ldr	r3, [r0]
-	and	r3, r4, r3
-	cmp	r3, #AT91C_PMC_MOSCS
-	bne	MOSCS_Loop
-
-
-/*-----------------------------------------------------------------------------
-;PMC Init Step 2.
-;------------------------------------------------------------------------------
-;- Setup PLLA
-;----------------------------------------------------------------------------*/
-	ldr	r1, =AT91C_CKGR_PLLAR
-	/* (18.432 MHz / 1) * 13 = 239 MHz */
-	ldr 	r0, =PLLAR_VAL
-	str	r0, [r1]
-
-	/* Reading the PMC Status register to detect */
-	/* when the PLLA is locked */
-	mov	r4, #AT91C_PMC_LOCKA
-	ldr	r0,=AT91C_PMC_SR
-MOSCS_Loop1:
-	ldr	r3, [r0]
-	and	r3, r4, r3
-	cmp	r3, #AT91C_PMC_LOCKA
-	bne	MOSCS_Loop1
-
-
-/*-----------------------------------------------------------------------------
-;PMC Init Step 3.
-;------------------------------------------------------------------------------
-;- Switch on the Main Oscillator 18.432 MHz
-;----------------------------------------------------------------------------*/
-Init_MCKR:
-
-	/* -Master Clock Controller register PMC_MCKR */
-	ldr	r0, =MCKR1_VAL
-	ldr	r1, =AT91C_PMC_MCKR
-	str	r0, [r1]
-
-	/* Reading the PMC Status register to detect */
-	/* when the Master clock is ready */
-	mov	r4, #AT91C_PMC_MCKRDY
-MCKRDY_Loop:
-	ldr	r1, =AT91C_PMC_SR
-	ldr	r3, [r1]
-	and	r3, r4, r3
-	cmp	r3, #AT91C_PMC_MCKRDY
-	bne	MCKRDY_Loop
-
-	ldr	r0, =MCKR2_VAL
-	ldr	r1, =AT91C_PMC_MCKR
-	str	r0, [r1]
-
-	/* Reading the PMC Status register to detect */
-	/* when the Master clock is ready */
-	mov	r4, #AT91C_PMC_MCKRDY
-MCKRDY_Loop1:
-	ldr	r1, =AT91C_PMC_SR
-	ldr	r3, [r1]
-	and	r3, r4, r3
-	cmp	r3, #AT91C_PMC_MCKRDY
-	bne	MCKRDY_Loop1
-
-/*-----------------------------------------------------------------------------
-;PMC Init Step 4.
-;------------------------------------------------------------------------------
-;- Setup PLLB
-;----------------------------------------------------------------------------*/
-	ldr	r1, = AT91C_PMC_PLLBR
-
-	/* 48.054857 MHz = 18432000 * 72 / 14 / 2 for USB) */
-	ldr 	r0, =PLLBR_VAL
-	str	r0, [r1]
-
-	/* Reading the PMC Status register to detect */
-	/* when the PLLB is locked */
-	mov	r4, #AT91C_PMC_LOCKB
-MOSCS_Loop2:
-	ldr	r1, = AT91C_PMC_SR
-	ldr	r3, [r1]
-	and	r3, r4, r3
-	cmp	r3, #AT91C_PMC_LOCKB
-	bne	MOSCS_Loop2
-
-	/* memory control configuration 2 */
-	ldr	r0, =SMRDATA1
-	ldr	r2, =SMRDATA2
-	ldr	r1, _TEXT_BASE
-	sub	r0, r0, r1
-	sub	r2, r2, r1
-	add	r0, r0, r5
-	add	r2, r2, r5
-
-2:
-	/* the address */
-	ldr	r1, [r0], #4
-	/* the value */
-	ldr	r3, [r0], #4
-	str	r3, [r1]
-	cmp	r2, r0
-	bne	2b
-
-	/* everything is fine now */
-	mov	pc, lr
-
-	.ltorg
-
-SMRDATA:
-	.word AT91C_WDTC_WDMR
-	.word WDTC_WDMR_VAL
-	.word AT91C_PIOD_PDR
-	.word PIOD_PDR_VAL1
-	.word AT91C_PIOD_PPUDR
-	.word PIOD_PPUDR_VAL
-	.word AT91C_PIOD_ASR
-	.word PIOD_PPUDR_VAL
-
-	.word AT91C_CCFG_EBI0CSA
-	.word MATRIX_EBI0CSA_VAL
-	.word AT91C_CCFG_EBI1CSA
-	.word MATRIX_EBI1CSA_VAL
-
-	/* flash */
-	.word AT91C_SMC0_CTRL0
-	.word SMC0_CTRL0_VAL
-
-	.word AT91C_SMC0_CYCLE0
-	.word SMC0_CYCLE0_VAL
-
-	.word AT91C_SMC0_PULSE0
-	.word SMC0_PULSE0_VAL
-
-	.word AT91C_SMC0_SETUP0
-	.word SMC0_SETUP0_VAL
-
-SMRDATA1:
-
-	.word AT91C_SDRAMC0_MR
-	.word SDRC_MR_VAL1
-	.word AT91C_SDRAMC0_TR
-	.word SDRC_TR_VAL1
-	.word AT91C_SDRAMC0_CR
-	.word SDRC_CR_VAL
-	.word AT91C_SDRAMC0_MDR
-	.word SDRC_MDR_VAL
-	.word AT91C_SDRAMC0_MR
-	.word SDRC_MR_VAL2
-	.word SDRAM
-	.word SDRAM_VAL1
-	.word AT91C_SDRAMC0_MR
-	.word SDRC_MR_VAL3
-	.word SDRAM
-	.word SDRAM_VAL2
-	.word SDRAM
-	.word SDRAM_VAL3
-	.word SDRAM
-	.word SDRAM_VAL4
-	.word SDRAM
-	.word SDRAM_VAL5
-	.word SDRAM
-	.word SDRAM_VAL6
-	.word SDRAM
-	.word SDRAM_VAL7
-	.word SDRAM
-	.word SDRAM_VAL8
-	.word SDRAM
-	.word SDRAM_VAL9
-	.word AT91C_SDRAMC0_MR
-	.word SDRC_MR_VAL4
-	.word SDRAM
-	.word SDRAM_VAL10
-	.word AT91C_SDRAMC0_MR
-	.word SDRC_MR_VAL5
-	.word SDRAM
-	.word SDRAM_VAL11
-	.word AT91C_SDRAMC0_TR
-	.word SDRC_TR_VAL2
-	.word SDRAM
-	.word SDRAM_VAL12
-	/* User reset enable */
-	.word AT91C_RSTC_RMR
-	.word RSTC_RMR_VAL
-	/* MATRIX_MCFG - REMAP all masters */
-
-SMRDATA2:
-	.word 0
diff --git a/board/pm9263/Makefile b/board/pm9263/Makefile
index 73ef72e210..eb072c0161 100644
--- a/board/pm9263/Makefile
+++ b/board/pm9263/Makefile
@@ -1,2 +1 @@
-obj-y += lowlevel_init.o
 obj-y += init.o
diff --git a/board/pm9263/config.h b/board/pm9263/config.h
index afd8563212..9a9c5cdcb7 100644
--- a/board/pm9263/config.h
+++ b/board/pm9263/config.h
@@ -3,4 +3,124 @@
 
 #define AT91_MASTER_CLOCK  99328000        /* peripheral = main / 2 */
 
+#define MASTER_PLL_DIV		6
+#define MASTER_PLL_MUL		65
+#define MAIN_PLL_DIV		2	/* 2 or 4 */
+
+/* clocks */
+#define CONFIG_SYS_MOR_VAL						\
+		(AT91_PMC_MOSCEN |					\
+		 (255 << 8))		/* Main Oscillator Start-up Time */
+#define CONFIG_SYS_PLLAR_VAL						\
+		(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
+		 AT91_PMC_OUT |						\
+		 AT91_PMC_PLLCOUNT |	/* PLL Counter */		\
+		 (2 << 28) |		/* PLL Clock Frequency Range */	\
+		 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
+
+#if (MAIN_PLL_DIV == 2)
+/* PCK/2 = MCK Master Clock from PLLA */
+#define	CONFIG_SYS_MCKR1_VAL		\
+		(AT91_PMC_CSS_SLOW |	\
+		 AT91_PMC_PRES_1 |	\
+		 AT91SAM9_PMC_MDIV_2 |	\
+		 AT91_PMC_PDIV_1)
+/* PCK/2 = MCK Master Clock from PLLA */
+#define	CONFIG_SYS_MCKR2_VAL		\
+		(AT91_PMC_CSS_PLLA |	\
+		 AT91_PMC_PRES_1 |	\
+		 AT91SAM9_PMC_MDIV_2 |	\
+		 AT91_PMC_PDIV_1)
+#else
+/* PCK/4 = MCK Master Clock from PLLA */
+#define	CONFIG_SYS_MCKR1_VAL			\
+		(AT91_PMC_CSS_SLOW |		\
+		 AT91_PMC_PRES_1 |		\
+		 AT91RM9200_PMC_MDIV_3 |	\
+		 AT91_PMC_PDIV_1)
+/* PCK/4 = MCK Master Clock from PLLA */
+#define	CONFIG_SYS_MCKR2_VAL			\
+		(AT91_PMC_CSS_PLLA |		\
+		 AT91_PMC_PRES_1 |		\
+		 AT91RM9200_PMC_MDIV_3 |	\
+		 AT91_PMC_PDIV_1)
+#endif
+/* define PDC[31:16] as DATA[31:16] */
+#define CONFIG_SYS_PIOD_PDR_VAL1	0xFFFF0000
+/* no pull-up for D[31:16] */
+#define CONFIG_SYS_PIOD_PPUDR_VAL	0xFFFF0000
+/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
+#define CONFIG_SYS_MATRIX_EBI0CSA_VAL					\
+	(AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V |	\
+	 AT91_MATRIX_EBI0_CS1A_SDRAMC)
+
+/* SDRAM */
+/* SDRAMC_MR Mode register */
+#define CONFIG_SYS_SDRC_MR_VAL1		0
+/* SDRAMC_TR - Refresh Timer register */
+#define CONFIG_SYS_SDRC_TR_VAL1		0x3AA
+/* SDRAMC_CR - Configuration register*/
+#define CONFIG_SYS_SDRC_CR_VAL							\
+		(AT91_SDRAMC_NC_9 |						\
+		 AT91_SDRAMC_NR_13 |						\
+		 AT91_SDRAMC_NB_4 |						\
+		 AT91_SDRAMC_CAS_2 |						\
+		 AT91_SDRAMC_DBW_32 |						\
+		 (2 <<  8) |	/* tWR -  Write Recovery Delay */		\
+		 (7 << 12) |	/* tRC -  Row Cycle Delay */			\
+		 (2 << 16) |	/* tRP -  Row Precharge Delay */		\
+		 (2 << 20) |	/* tRCD - Row to Column Delay */		\
+		 (5 << 24) |	/* tRAS - Active to Precharge Delay */		\
+		 (8 << 28))	/* tXSR - Exit Self Refresh to Active Delay */
+
+/* Memory Device Register -> SDRAM */
+#define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
+#define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
+#define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
+#define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
+#define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
+#define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
+#define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */
+
+/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
+#define CONFIG_SYS_SMC0_SETUP0_VAL					\
+		(AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) |	\
+		 AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
+#define CONFIG_SYS_SMC0_PULSE0_VAL					\
+		(AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) |	\
+		 AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
+#define CONFIG_SYS_SMC0_CYCLE0_VAL	\
+		(AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
+#define CONFIG_SYS_SMC0_MODE0_VAL				\
+		(AT91_SMC_READMODE | AT91_SMC_WRITEMODE |	\
+		 AT91_SMC_DBW_16 |				\
+		 AT91_SMC_TDFMODE |				\
+		 AT91_SMC_TDF_(6))
+
+/* user reset enable */
+#define CONFIG_SYS_RSTC_RMR_VAL			\
+		(AT91_RSTC_KEY |		\
+		AT91_RSTC_PROCRST |		\
+		AT91_RSTC_RSTTYP_WAKEUP |	\
+		AT91_RSTC_RSTTYP_WATCHDOG)
+
+/* Disable Watchdog */
+#define CONFIG_SYS_WDTC_WDMR_VAL				\
+		(AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |	\
+		 AT91_WDT_WDV |					\
+		 AT91_WDT_WDDIS |				\
+		 AT91_WDT_WDD)
+
+
 #endif	/* __CONFIG_H */
diff --git a/board/pm9263/init.c b/board/pm9263/init.c
index 67c5ae7ddf..0d3d6d9412 100644
--- a/board/pm9263/init.c
+++ b/board/pm9263/init.c
@@ -33,11 +33,14 @@
 #include <asm/hardware.h>
 #include <nand.h>
 #include <linux/mtd/nand.h>
+#include <asm/arch/at91_pmc.h>
 #include <asm/arch/board.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
 
 static struct device_d cfi_dev = {
 	.name     = "cfi_flash",
-	.map_base = 0x10000000,
+	.map_base = AT91_CHIPSELECT_0,
 	.size     = 4 * 1024 * 1024,
 };
 
@@ -48,30 +51,16 @@ static struct at91_ether_platform_data macb_pdata = {
 
 static int pm9263_devices_init(void)
 {
-	u32 pe = AT91C_PC25_ERXDV;
+	/*
+	 * PB27 enables the 50MHz oscillator for Ethernet PHY
+	 * 1 - enable
+	 * 0 - disable
+	 */
+	at91_set_gpio_output(AT91_PIN_PB27, 1);
+	at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */
 
-	writel(pe, AT91C_BASE_PIOC + PIO_BSR(0));
-	writel(pe, AT91C_BASE_PIOC + PIO_PDR(0));
-
-	pe =	AT91C_PE21_ETXCK |
-		AT91C_PE23_ETX0 |
-		AT91C_PE24_ETX1 |
-		AT91C_PE25_ERX0 |
-		AT91C_PE26_ERX1 |
-		AT91C_PE27_ERXER |
-		AT91C_PE28_ETXEN |
-		AT91C_PE29_EMDC |
-		AT91C_PE30_EMDIO;
-
-	writel(pe, AT91C_BASE_PIOE + PIO_ASR(0));
-	writel(pe, AT91C_BASE_PIOE + PIO_PDR(0));
-
-	/* set PB27 to '1',  enable 50MHz oscillator */
-	writel(AT91C_PIO_PB27, AT91C_BASE_PIOB + PIO_PER(0));
-	writel(AT91C_PIO_PB27, AT91C_BASE_PIOB + PIO_OER(0));
-	writel(AT91C_PIO_PB27, AT91C_BASE_PIOB + PIO_SODR(0));
-
-	writel(1 << AT91C_ID_EMAC, AT91C_PMC_PCER);
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
 
 	at91_add_device_sdram(64 * 1024 * 1024);
 	at91_add_device_eth(&macb_pdata);
@@ -80,7 +69,7 @@ static int pm9263_devices_init(void)
 	devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
 	devfs_add_partition("nor0", 0x40000, 0x10000, PARTITION_FIXED, "env0");
 
-	armlinux_set_bootparams((void *)0x20000100);
+	armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
 	armlinux_set_architecture(MACH_TYPE_PM9263);
 
 	return 0;
@@ -90,9 +79,7 @@ device_initcall(pm9263_devices_init);
 
 static int pm9263_console_init(void)
 {
-	writel(AT91C_PC31_DTXD | AT91C_PC30_DRXD, AT91C_PIOC_PDR);
-
-	at91_register_uart(0);
+	at91_register_uart(0, 0);
 	return 0;
 }
 
diff --git a/board/pm9263/lowlevel_init.S b/board/pm9263/lowlevel_init.S
deleted file mode 100644
index 2967035404..0000000000
--- a/board/pm9263/lowlevel_init.S
+++ /dev/null
@@ -1,322 +0,0 @@
-/*
- * Board specific setup info
- *
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm/arch/hardware.h>
-
-#define SDRAM 0x20000000		/* address of the SDRAM */
-
-/* values */
-
-/* clocks */
-#define MOR_VAL 0x00002001		/* CKGR_MOR - enable main osc. */
-#define PLLAR_VAL (0x2000BF00 | ((MASTER_PLL_MUL - 1)<< 16) | (MASTER_PLL_DIV))
-/* #define PLLAR_VAL 0x200CBF01 */	/* 239.616000 MHz for PCK */
-#define PLLBR_VAL 0x10483E0E		/* 48.054857 MHz for USB) */
-
-#define MCKR1_VAL 0x00000100		/* PCK/2 = MCK Master Clock from PLLA*/
-#define MCKR2_VAL 0x00000102		/* PCK/2 = MCK Master Clock from PLLA*/
-
-#define WDTC_WDMR_VAL 0x3fff8fff	/* disable watchdog */
-#define PIOD_PDR_VAL1 0xFFFF0000	/* define PDC[31:16] as DATA[31:16] */
-#define PIOD_PPUDR_VAL 0xFFFF0000	/* no pull-up for D[31:16] */
-#define MATRIX_EBI0CSA_VAL 0x0001010A	/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
-/*#define MATRIX_EBI1CSA_VAL 0x00000000	/* EBI1_CSA, 1.8V memory*/
-#define MATRIX_EBI1CSA_VAL 0x00010100	/* EBI1_CSA, 3.3v, no pull-ups*/
-
-/* SDRAM */
-#define SDRC_MR_VAL1 0			/* SDRAMC_MR Mode register */
-#define SDRC_TR_VAL1 0x13C		/* SDRAMC_TR - Refresh Timer register*/
-/*#define SDRC_CR_VAL 0x85237279*/	/* SDRAMC_CR - Configuration register*/
-/*#define SDRC_CR_VAL 0x85227259  CL2 */
-#define SDRC_CR_VAL   0x85227279 /*CL3*/
-#define SDRC_MDR_VAL 0			/*  Memory Device Register -> SDRAM */
-#define SDRC_MR_VAL2 0x00000002		/*  SDRAMC_MR */
-#define SDRAM_VAL1 0			/*  SDRAM_BASE */
-#define SDRC_MR_VAL3 4			/*  SDRC_MR */
-#define SDRAM_VAL2 0			/*  SDRAM_BASE */
-#define SDRAM_VAL3 0			/*  SDRAM_BASE */
-#define SDRAM_VAL4 0			/*  SDRAM_BASE */
-#define SDRAM_VAL5 0			/*  SDRAM_BASE */
-#define SDRAM_VAL6 0			/*  SDRAM_BASE */
-#define SDRAM_VAL7 0			/*  SDRAM_BASE */
-#define SDRAM_VAL8 0			/*  SDRAM_BASE */
-#define SDRAM_VAL9 0			/*  SDRAM_BASE */
-#define SDRC_MR_VAL4 3			/*  SDRC_MR */
-#define SDRAM_VAL10 0			/* SDRAM_BASE */
-#define SDRC_MR_VAL5 0			/*  SDRC_MR */
-#define SDRAM_VAL11 0			/*  SDRAM_BASE */
-#define SDRC_TR_VAL2 1200		/* SDRAM_TR */
-#define SDRAM_VAL12 0			/*  SDRAM_BASE */
-
-/* setup CS0 (NOR Flash) - 16-bit, 15 WS */
-#define SMC0_SETUP0_VAL 0x0A0A0A0A	/*  SMC_SETUP */
-#define SMC0_PULSE0_VAL 0x0B0B0B0B	/*  SMC_PULSE */
-#define SMC0_CYCLE0_VAL 0x00160016	/*  SMC_CYCLE */
-#define SMC0_CTRL0_VAL 0x00161003	/*  SMC_MODE */
-
-#define RSTC_RMR_VAL 0xA5000301		/* user reset enable */
-
-#define MASTER_PLL_MUL                162
-#define MASTER_PLL_DIV                15
-
-_TEXT_BASE:
-	.word	TEXT_BASE
-
-.globl board_init_lowlevel
-board_init_lowlevel:
-
-	mov	r5, pc		// r5 = POS1 + 4 current
-POS1:
-	ldr	r0, =POS1	// r0 = POS1 compile
-	ldr	r2, _TEXT_BASE
-	sub	r0, r0, r2	// r0 = POS1-_TEXT_BASE (POS1 relative)
-	sub	r5, r5, r0	// r0 = TEXT_BASE-1
-	sub	r5, r5, #4	// r1 = text base - current
-
-	/* memory control configuration 1 */
-	ldr	r0, =SMRDATA
-	ldr	r2, =SMRDATA1
-	ldr	r1, _TEXT_BASE
-	sub	r0, r0, r1
-	sub	r2, r2, r1
-	add	r0, r0, r5
-	add	r2, r2, r5
-0:
-	/* the address */
-	ldr	r1, [r0], #4
-	/* the value */
-	ldr	r3, [r0], #4
-	str	r3, [r1]
-	cmp	r2, r0
-	bne	0b
-
-/*-----------------------------------------------------------------------------
-;PMC Init Step 1.
-;------------------------------------------------------------------------------
-;- Enable the Main Oscillator
-;----------------------------------------------------------------------------*/
-	/* Test if main oscillator is enabled */
-	ldr 	r0,=AT91C_PMC_SR
-	ldr 	r1, [r0]
-	ldr 	r2,=AT91C_PMC_MOSCS
-	ands 	r1, r1, r2
-
-	ldr     r1, =AT91C_CKGR_MOR
-
-	/* Main oscillator Enable register PMC_MOR: */
-	/* Enable main oscillator, OSCOUNT = 0xFF */
-	ldr 	r0, =0x0000FF01
-	str     r0, [r1]
-
-	/* Reading the PMC Status register to detect when the */
-	/* Main Oscillator is enabled */
-	mov     r4, #AT91C_PMC_MOSCS
-	ldr     r0,=AT91C_PMC_SR
-MOSCS_Loop:
-	ldr	r3, [r0]
-	and     r3, r4, r3
-	cmp     r3, #AT91C_PMC_MOSCS
-	bne     MOSCS_Loop
-
-
-/*-----------------------------------------------------------------------------
-;PMC Init Step 2.
-;------------------------------------------------------------------------------
-;- Setup PLLA
-;----------------------------------------------------------------------------*/
-	ldr     r1, =AT91C_CKGR_PLLAR
-	/* (18.432 MHz / 1) * 13 = 239 MHz */
-	ldr 	r0, =PLLAR_VAL
-	str     r0, [r1]
-
-	/* Reading the PMC Status register to detect */
-	/* when the PLLA is locked */
-	mov     r4, #AT91C_PMC_LOCKA
-	ldr     r0,=AT91C_PMC_SR
-MOSCS_Loop1:
-	ldr     r3, [r0]
-	and     r3, r4, r3
-	cmp     r3, #AT91C_PMC_LOCKA
-	bne     MOSCS_Loop1
-
-
-/*-----------------------------------------------------------------------------
-;PMC Init Step 3.
-;------------------------------------------------------------------------------
-;- Switch on the Main Oscillator 18.432 MHz
-;----------------------------------------------------------------------------*/
-Init_MCKR:
-
-	/* -Master Clock Controller register PMC_MCKR */
-	ldr     r0, =0x100
-	ldr     r1, =AT91C_PMC_MCKR
-	str     r0, [r1]
-
-	/* Reading the PMC Status register to detect */
-	/* when the Master clock is ready */
-	mov     r4, #AT91C_PMC_MCKRDY
-MCKRDY_Loop:
-	ldr	r1, =AT91C_PMC_SR
-	ldr     r3, [r1]
-	and     r3, r4, r3
-	cmp     r3, #AT91C_PMC_MCKRDY
-	bne     MCKRDY_Loop
-
-	ldr     r0, =0x102
-	ldr	r1, =AT91C_PMC_MCKR
-	str     r0, [r1]
-
-	/* Reading the PMC Status register to detect */
-	/* when the Master clock is ready */
-	mov     r4, #AT91C_PMC_MCKRDY
-MCKRDY_Loop1:
-	ldr	r1, =AT91C_PMC_SR
-	ldr     r3, [r1]
-	and     r3, r4, r3
-	cmp     r3, #AT91C_PMC_MCKRDY
-	bne     MCKRDY_Loop1
-
-/*-----------------------------------------------------------------------------
-;PMC Init Step 4.
-;------------------------------------------------------------------------------
-;- Setup PLLB
-;----------------------------------------------------------------------------*/
-	ldr     r1, = AT91C_PMC_PLLBR
-
-	/* 48.054857 MHz = 18432000 * 72 / 14 / 2 for USB) */
-	ldr 	r0, =PLLBR_VAL
-	str     r0, [r1]
-
-	/* Reading the PMC Status register to detect */
-	/* when the PLLB is locked */
-	mov     r4, #AT91C_PMC_LOCKB
-MOSCS_Loop2:
-	ldr     r1, = AT91C_PMC_SR
-	ldr     r3, [r1]
-	and     r3, r4, r3
-	cmp     r3, #AT91C_PMC_LOCKB
-	bne     MOSCS_Loop2
-
-	/* memory control configuration 2 */
-	ldr	r0, =SMRDATA1
-	ldr	r2, =SMRDATA2
-	ldr	r1, _TEXT_BASE
-	sub	r0, r0, r1
-	sub	r2, r2, r1
-	add	r0, r0, r5
-	add	r2, r2, r5
-
-2:
-	/* the address */
-	ldr	r1, [r0], #4
-	/* the value */
-	ldr	r3, [r0], #4
-	str	r3, [r1]
-	cmp	r2, r0
-	bne	2b
-
-	/* everything is fine now */
-	mov	pc, lr
-
-	.ltorg
-
-SMRDATA:
-	.word AT91C_WDTC_WDMR
-	.word WDTC_WDMR_VAL
-	.word AT91C_PIOD_PDR
-	.word PIOD_PDR_VAL1
-	.word AT91C_PIOD_PPUDR
-	.word PIOD_PPUDR_VAL
-	.word AT91C_PIOD_ASR
-	.word PIOD_PPUDR_VAL
-
-	.word AT91C_CCFG_EBI0CSA
-	.word MATRIX_EBI0CSA_VAL
-	.word AT91C_CCFG_EBI1CSA
-	.word MATRIX_EBI1CSA_VAL
-
-	/* flash */
-	.word AT91C_SMC0_CTRL0
-	.word SMC0_CTRL0_VAL
-
-	.word AT91C_SMC0_CYCLE0
-	.word SMC0_CYCLE0_VAL
-
-	.word AT91C_SMC0_PULSE0
-	.word SMC0_PULSE0_VAL
-
-	.word AT91C_SMC0_SETUP0
-	.word SMC0_SETUP0_VAL
-
-SMRDATA1:
-
-	.word AT91C_SDRAMC0_MR
-	.word SDRC_MR_VAL1
-	.word AT91C_SDRAMC0_TR
-	.word SDRC_TR_VAL1
-	.word AT91C_SDRAMC0_CR
-	.word SDRC_CR_VAL
-	.word AT91C_SDRAMC0_MDR
-	.word SDRC_MDR_VAL
-	.word AT91C_SDRAMC0_MR
-	.word SDRC_MR_VAL2
-	.word SDRAM
-	.word SDRAM_VAL1
-	.word AT91C_SDRAMC0_MR
-	.word SDRC_MR_VAL3
-	.word SDRAM
-	.word SDRAM_VAL2
-	.word SDRAM
-	.word SDRAM_VAL3
-	.word SDRAM
-	.word SDRAM_VAL4
-	.word SDRAM
-	.word SDRAM_VAL5
-	.word SDRAM
-	.word SDRAM_VAL6
-	.word SDRAM
-	.word SDRAM_VAL7
-	.word SDRAM
-	.word SDRAM_VAL8
-	.word SDRAM
-	.word SDRAM_VAL9
-	.word AT91C_SDRAMC0_MR
-	.word SDRC_MR_VAL4
-	.word SDRAM
-	.word SDRAM_VAL10
-	.word AT91C_SDRAMC0_MR
-	.word SDRC_MR_VAL5
-	.word SDRAM
-	.word SDRAM_VAL11
-	.word AT91C_SDRAMC0_TR
-	.word SDRC_TR_VAL2
-	.word SDRAM
-	.word SDRAM_VAL12
-	/* User reset enable*/
-	.word AT91C_RSTC_RMR
-	.word RSTC_RMR_VAL
-	/* MATRIX_MCFG - REMAP all masters */
-
-SMRDATA2:
-	.word 0
-