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| author | Lucas Stach <l.stach@pengutronix.de> | 2017-03-01 15:26:41 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2017-03-03 07:06:06 +0100 |
| commit | 7497685b05706ee521ff2b38096c878e19bfcd61 (patch) | |
| tree | 2b58424d41141611bc99fefb4f805626d8789f46 /commands | |
| parent | d92ce9b36a363ead3549343be800fe1dfac8ca2c (diff) | |
| download | barebox-7497685b05706ee521ff2b38096c878e19bfcd61.tar.gz barebox-7497685b05706ee521ff2b38096c878e19bfcd61.tar.xz | |
ARM: execute DMB before trying to flush cache
The CPU write buffer needs to be coherent with the cache, otherwise
we might flush stale entries with the actual data stuck in the cache.
This is really important on newer CPU core with bigger write buffers.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'commands')
0 files changed, 0 insertions, 0 deletions