summaryrefslogtreecommitdiffstats
path: root/common/Kconfig
diff options
context:
space:
mode:
authorSteffen Trumtrar <s.trumtrar@pengutronix.de>2017-04-28 16:41:41 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2017-05-03 13:51:22 +0200
commitd5c8bc3ff1a795cb9ef44abd518f5dae6f9000fa (patch)
treea3dbd48b1feef91687bd75e9227870debbbbf9cb /common/Kconfig
parentdb3feb61d19060a0589f3906a8a081bebd934ace (diff)
downloadbarebox-d5c8bc3ff1a795cb9ef44abd518f5dae6f9000fa.tar.gz
ARM: socfpga: add arria10 support
Arria10 is a SoC + FPGA like the Cyclone5 SoCFPGA that is already supported in barebox. Both a the same in some parts, but totaly different in others. Most of the hardware blocks are the same in the SoC parts. The OCRAM is larger on the Arria10 and the SDRAM controller is different. The serial core only supports 32bit accesses (different to the 8bit accesses on the Cyclone5). As Arria10 has 256KB of OCRAM, it is possible to fit a larger barebox (and/or use PBL) instead of the two stage bootprocess used on the Cyclone5 and its 64KB OCRAM. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'common/Kconfig')
-rw-r--r--common/Kconfig11
1 files changed, 10 insertions, 1 deletions
diff --git a/common/Kconfig b/common/Kconfig
index 4c7a2d2..459f0b1 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -1129,6 +1129,13 @@ config DEBUG_SOCFPGA_UART0
Say Y here if you want kernel low-level debugging support
on SOCFPGA(Cyclone 5 and Arria 5) based platforms.
+config DEBUG_SOCFPGA_UART1
+ bool "Use SOCFPGA UART1 for low-level debug"
+ depends on ARCH_SOCFPGA
+ help
+ Say Y here if you want kernel low-level debugging support
+ on SOCFPGA(Arria 10) based platforms.
+
endchoice
@@ -1175,11 +1182,13 @@ config DEBUG_ROCKCHIP_UART_PORT
config DEBUG_SOCFPGA_UART_PHYS_ADDR
hex "Physical base address of debug UART" if DEBUG_LL
default 0xffc02000 if DEBUG_SOCFPGA_UART0
+ default 0xffc02100 if DEBUG_SOCFPGA_UART1
depends on ARCH_SOCFPGA
config DEBUG_SOCFPGA_UART_CLOCK
int "SoCFPGA UART debug clock" if DEBUG_LL
- default 100000000
+ default 100000000 if ARCH_SOCFPGA_CYCLONE5
+ default 50000000 if ARCH_SOCFPGA_ARRIA10
depends on ARCH_SOCFPGA
help
Choose UART root clock.