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| author | Stefan Roese <sr@denx.de> | 2006-11-27 14:11:22 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2006-11-27 14:11:22 +0100 |
| commit | 48c7d6dba9140869a1d644248aa8cfabe01c98a6 (patch) | |
| tree | e5dcf79067eb653dcfa5e87667d4af204c0fb554 /cpu/ppc4xx | |
| parent | dfc8a9ee0040e53ada125a3c52f241e37f09cf28 (diff) | |
| parent | 3b58d9459081ae33885335c645fc0b865584ae4e (diff) | |
| download | barebox-48c7d6dba9140869a1d644248aa8cfabe01c98a6.tar.gz barebox-48c7d6dba9140869a1d644248aa8cfabe01c98a6.tar.xz | |
Merge with /home/stefan/git/u-boot/denx
Diffstat (limited to 'cpu/ppc4xx')
| -rw-r--r-- | cpu/ppc4xx/start.S | 23 |
1 files changed, 12 insertions, 11 deletions
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 3fe13daaf3..8e000d3092 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -204,6 +204,18 @@ _start_440: mfspr r1,mcsr mtspr mcsr,r1 #endif + + /*----------------------------------------------------------------*/ + /* CCR0 init */ + /*----------------------------------------------------------------*/ + /* Disable store gathering & broadcast, guarantee inst/data + * cache block touch, force load/store alignment + * (see errata 1.12: 440_33) + */ + lis r1,0x0030 /* store gathering & broadcast disable */ + ori r1,r1,0x6000 /* cache touch */ + mtspr ccr0,r1 + /*----------------------------------------------------------------*/ /* Initialize debug */ /*----------------------------------------------------------------*/ @@ -225,17 +237,6 @@ _start_440: mtspr dbsr,r1 /* Clear all valid bits */ skip_debug_init: - /*----------------------------------------------------------------*/ - /* CCR0 init */ - /*----------------------------------------------------------------*/ - /* Disable store gathering & broadcast, guarantee inst/data - * cache block touch, force load/store alignment - * (see errata 1.12: 440_33) - */ - lis r1,0x0030 /* store gathering & broadcast disable */ - ori r1,r1,0x6000 /* cache touch */ - mtspr ccr0,r1 - #if defined (CONFIG_440SPE) /*----------------------------------------------------------------+ | Initialize Core Configuration Reg1. |