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| author | Stefan Roese <sr@denx.de> | 2006-11-27 14:46:06 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2006-11-27 14:46:06 +0100 |
| commit | ec0c2ec725aec9524a177a77ce75559e644a931a (patch) | |
| tree | 980ba07ed67b7e2b9276973c487f4b0b74f9eb24 /cpu/ppc4xx | |
| parent | 1c2ce2262069510f31c7d3fd7efd3d58b8c0c148 (diff) | |
| download | barebox-ec0c2ec725aec9524a177a77ce75559e644a931a.tar.gz barebox-ec0c2ec725aec9524a177a77ce75559e644a931a.tar.xz | |
[PATCH] Remove testing 4xx enet PHY setup
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu/ppc4xx')
| -rw-r--r-- | cpu/ppc4xx/4xx_enet.c | 17 |
1 files changed, 1 insertions, 16 deletions
diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 8c517baf3b..7a2483c3cd 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -560,22 +560,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) * otherwise, just check the speeds & feeds */ if (hw_p->first_init == 0) { -#if defined(CONFIG_88E1111_CLK_DELAY) - /* - * On some boards (e.g. ALPR) the Marvell 88E1111 PHY needs - * the "RGMII transmit timing control" and "RGMII receive - * timing control" bits set, so that Gbit communication works - * without problems. - * Also set the "Transmitter disable" to 1 to enable the - * transmitter. - * After setting these bits a soft-reset must occur for this - * change to become active. - */ - miiphy_read (dev->name, reg, 0x14, ®_short); - reg_short |= (1 << 7) | (1 << 1) | (1 << 0); - miiphy_write (dev->name, reg, 0x14, reg_short); -#endif -#if defined(CONFIG_M88E1111_PHY) /* test-only: merge with CONFIG_88E1111_CLK_DELAY !!! */ +#if defined(CONFIG_M88E1111_PHY) miiphy_write (dev->name, reg, 0x14, 0x0ce3); miiphy_write (dev->name, reg, 0x18, 0x4101); miiphy_write (dev->name, reg, 0x09, 0x0e00); |