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| author | Andrey Panov <rockford@yandex.ru> | 2015-03-04 23:11:33 +0300 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2015-03-05 09:11:34 +0100 |
| commit | 9e3ce4eee64ff143b280efbae1582f20261a3187 (patch) | |
| tree | 84949372cd7a10404cea3dc20fe4efab0132b4bd /drivers/clk/clk-divider.c | |
| parent | 7baf7df9fd46fa3a3439a50f49de2ccdc48e2239 (diff) | |
| download | barebox-9e3ce4eee64ff143b280efbae1582f20261a3187.tar.gz barebox-9e3ce4eee64ff143b280efbae1582f20261a3187.tar.xz | |
CLK: clk-divider: Respect CLK_DIVIDER_HIWORD_MASK flag
It is required for Rockchip SoCs where clock settings registers have
write-enable mask in high word.
Signed-off-by: Andrey Panov <rockford@yandex.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/clk/clk-divider.c')
| -rw-r--r-- | drivers/clk/clk-divider.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 506a9668a9..eb4833441a 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -197,6 +197,10 @@ static int clk_divider_set_rate(struct clk *clk, unsigned long rate, val = readl(divider->reg); val &= ~(div_mask(divider) << divider->shift); val |= value << divider->shift; + + if (clk->flags & CLK_DIVIDER_HIWORD_MASK) + val |= div_mask(divider) << (divider->shift + 16); + writel(val, divider->reg); return 0; |