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author | Lucas Stach <dev@lynxeye.de> | 2013-06-30 23:08:44 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2013-07-02 08:36:09 +0200 |
commit | c780cd044e9f87f70c07a85103e16c35e83824e1 (patch) | |
tree | afa356ad9f45b4f7a25e3a3a3c0f4ea4a4649b9b /drivers/clk/clk-gate.c | |
parent | b0d851d9517e113481b3c32bf90006b3f2d7503e (diff) | |
download | barebox-c780cd044e9f87f70c07a85103e16c35e83824e1.tar.gz barebox-c780cd044e9f87f70c07a85103e16c35e83824e1.tar.xz |
tegra: change clocksource driver to be more lowlevel
In order to properly bring up the system PLLs we need a reliable
clocksource. To break the circular dependency between the clocksource
and the CAR driver, get the OSC frequency with a lowlevel function.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/clk/clk-gate.c')
0 files changed, 0 insertions, 0 deletions