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authorSascha Hauer <s.hauer@pengutronix.de>2017-02-02 08:43:04 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2017-02-06 07:32:22 +0100
commitbce79428773b87e0fe84be07048992c98249581a (patch)
tree75e362a1c80110fc3f520fdb1da30fbe3d28a252 /drivers/clk/imx/clk-imx7.c
parentf5409645e9977727d4512a474cbdfe9caae40790 (diff)
downloadbarebox-bce79428773b87e0fe84be07048992c98249581a.tar.gz
clk: i.MX7: do clock reparenting when all clocks are initialized
By the time the i.MX7 clock driver probes the fixed clocks which are the roots of the clock tree are not yet present, so reparenting especially to one of the fixed clocks does not work. Move the tree setup to a later initcall when the fixed clocks are there. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/clk/imx/clk-imx7.c')
-rw-r--r--drivers/clk/imx/clk-imx7.c31
1 files changed, 23 insertions, 8 deletions
diff --git a/drivers/clk/imx/clk-imx7.c b/drivers/clk/imx/clk-imx7.c
index 45c5a46..383b685 100644
--- a/drivers/clk/imx/clk-imx7.c
+++ b/drivers/clk/imx/clk-imx7.c
@@ -383,11 +383,12 @@ static struct clk ** const uart_clks[] __initconst = {
NULL
};
+static int imx7_clk_initialized;
+
static int imx7_ccm_probe(struct device_d *dev)
{
struct resource *iores;
void __iomem *base, *anatop_base, *ccm_base;
- int i;
anatop_base = IOMEM(MX7_ANATOP_BASE_ADDR);
iores = dev_request_mem_resource(dev, 0);
@@ -418,13 +419,6 @@ static int imx7_ccm_probe(struct device_d *dev)
clks[IMX7D_PLL_AUDIO_MAIN_BYPASS] = imx_clk_mux_p("pll_audio_main_bypass", base + 0xf0, 16, 1, pll_audio_bypass_sel, ARRAY_SIZE(pll_audio_bypass_sel));
clks[IMX7D_PLL_VIDEO_MAIN_BYPASS] = imx_clk_mux_p("pll_video_main_bypass", base + 0x130, 16, 1, pll_video_bypass_sel, ARRAY_SIZE(pll_video_bypass_sel));
- clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]);
- clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]);
- clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]);
- clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MAIN]);
- clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]);
- clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]);
-
clks[IMX7D_PLL_ARM_MAIN_CLK] = imx_clk_gate("pll_arm_main_clk", "pll_arm_main_bypass", base + 0x60, 13);
clks[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_gate("pll_dram_main_clk", "pll_dram_main_bypass", base + 0x70, 13);
clks[IMX7D_PLL_SYS_MAIN_CLK] = imx_clk_gate("pll_sys_main_clk", "pll_sys_main_bypass", base + 0xb0, 13);
@@ -848,9 +842,29 @@ static int imx7_ccm_probe(struct device_d *dev)
clk_data.clk_num = ARRAY_SIZE(clks);
of_clk_add_provider(dev->device_node, of_clk_src_onecell_get, &clk_data);
+ imx7_clk_initialized = 1;
+
+ return 0;
+}
+
+static int imx7_clk_setup(void)
+{
+ int i;
+
+ if (!imx7_clk_initialized)
+ return 0;
+
+ clks[IMX7D_OSC_24M_CLK] = clk_lookup("osc");
+
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
clk_enable(clks[clks_init_on[i]]);
+ clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]);
+ clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]);
+ clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]);
+ clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]);
+ clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]);
+
/* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */
clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
@@ -859,6 +873,7 @@ static int imx7_ccm_probe(struct device_d *dev)
return 0;
}
+postcore_initcall(imx7_clk_setup);
static __maybe_unused struct of_device_id imx7_ccm_dt_ids[] = {
{