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| author | Lucas Stach <dev@lynxeye.de> | 2013-06-30 23:08:49 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2013-07-02 08:36:09 +0200 |
| commit | 3cfd3be736edf6fea41b03c00023dba88a2ff11e (patch) | |
| tree | f2682998ec00ccf9d584f9e613c3f78731bc8436 /drivers/clk/tegra/clk-tegra20.c | |
| parent | c16730e3c66bcab245aac993ce924caa129ca23d (diff) | |
| download | barebox-3cfd3be736edf6fea41b03c00023dba88a2ff11e.tar.gz barebox-3cfd3be736edf6fea41b03c00023dba88a2ff11e.tar.xz | |
tegra: add peripheral clocks
Only UART clocks are included for now, but the code should cover
other peripherals needs, too.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra20.c')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra20.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 5f668cb325..e70f99a1fc 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -275,6 +275,28 @@ static void tegra20_pll_init(void) TEGRA_PLL_HAS_CPCON, pll_u_freq_table); } +static const char *mux_pllpcm_clkm[] = {"pll_p", "pll_c", "pll_m", "clk_m"}; + +static void tegra20_periph_init(void) +{ + /* peripheral clocks without a divider */ + clks[uarta] = tegra_clk_register_periph_nodiv("uarta", mux_pllpcm_clkm, + ARRAY_SIZE(mux_pllpcm_clkm), car_base, + CRC_CLK_SOURCE_UARTA, uarta, TEGRA_PERIPH_ON_APB); + clks[uartb] = tegra_clk_register_periph_nodiv("uartb", mux_pllpcm_clkm, + ARRAY_SIZE(mux_pllpcm_clkm), car_base, + CRC_CLK_SOURCE_UARTB, uartb, TEGRA_PERIPH_ON_APB); + clks[uartc] = tegra_clk_register_periph_nodiv("uartc", mux_pllpcm_clkm, + ARRAY_SIZE(mux_pllpcm_clkm), car_base, + CRC_CLK_SOURCE_UARTC, uartc, TEGRA_PERIPH_ON_APB); + clks[uartd] = tegra_clk_register_periph_nodiv("uartd", mux_pllpcm_clkm, + ARRAY_SIZE(mux_pllpcm_clkm), car_base, + CRC_CLK_SOURCE_UARTD, uartd, TEGRA_PERIPH_ON_APB); + clks[uarte] = tegra_clk_register_periph_nodiv("uarte", mux_pllpcm_clkm, + ARRAY_SIZE(mux_pllpcm_clkm), car_base, + CRC_CLK_SOURCE_UARTE, uarte, TEGRA_PERIPH_ON_APB); +} + static struct tegra_clk_init_table init_table[] = { {pll_p, clk_max, 216000000, 1}, {pll_p_out1, clk_max, 28800000, 1}, @@ -283,6 +305,11 @@ static struct tegra_clk_init_table init_table[] = { {pll_p_out4, clk_max, 24000000, 1}, {pll_c, clk_max, 600000000, 1}, {pll_c_out1, clk_max, 120000000, 1}, + {uarta, pll_p, 0, 1}, + {uartb, pll_p, 0, 1}, + {uartc, pll_p, 0, 1}, + {uartd, pll_p, 0, 1}, + {uarte, pll_p, 0, 1}, {clk_max, clk_max, 0, 0}, /* sentinel */ }; @@ -294,6 +321,7 @@ static int tegra20_car_probe(struct device_d *dev) tegra20_osc_clk_init(); tegra20_pll_init(); + tegra20_periph_init(); tegra_init_from_table(init_table, clks, clk_max); |