diff options
author | Lucas Stach <dev@lynxeye.de> | 2014-11-03 23:52:24 +0100 |
---|---|---|
committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-11-04 12:16:52 +0100 |
commit | c202b7c8d9e66082853ac1b131ddcedf53e9ca99 (patch) | |
tree | a99931c33f15981cb7c89b62bead145f2cc28a94 /drivers/clk/tegra/clk-tegra20.c | |
parent | 566c1630c3164e4e790ca1bfce462034a2639947 (diff) | |
download | barebox-c202b7c8d9e66082853ac1b131ddcedf53e9ca99.tar.gz barebox-c202b7c8d9e66082853ac1b131ddcedf53e9ca99.tar.xz |
clk: tegra: don't enable UART clocks by default
Now that we are registering a proper driver for the
UARTs we no longer need to enable the clocks unconditionally.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra20.c')
-rw-r--r-- | drivers/clk/tegra/clk-tegra20.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 5b4365d492..2ff42d8bdb 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -324,11 +324,11 @@ static struct tegra_clk_init_table init_table[] = { {TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1}, {TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 1}, {TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 1}, - {TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 1}, - {TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 0, 1}, - {TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 1}, - {TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 1}, - {TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 1}, + {TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 0}, + {TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 0, 0}, + {TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0}, + {TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0}, + {TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0}, {TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0}, {TEGRA20_CLK_SDMMC2, TEGRA20_CLK_PLL_P, 48000000, 0}, {TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0}, |