diff options
| author | Lucas Stach <dev@lynxeye.de> | 2014-11-02 21:13:48 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-11-04 12:16:51 +0100 |
| commit | 3e41e7561a1b3636140214d92401c10e15962d22 (patch) | |
| tree | 62dd8cf83bb00353f2be8e1a6a5ee4c0765c5963 /drivers/clk | |
| parent | c3b08ad1c611d0632a6515806dfdb20f7c27cdf1 (diff) | |
| download | barebox-3e41e7561a1b3636140214d92401c10e15962d22.tar.gz barebox-3e41e7561a1b3636140214d92401c10e15962d22.tar.xz | |
clk: tegra: slow down MSELECT to 102MHz
Don't know where I got the 204MHZ previously, but
102MHz is the official supported maximum.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra124.c | 2 | ||||
| -rw-r--r-- | drivers/clk/tegra/clk-tegra30.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index 7426b52aac..d597a239b9 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -321,7 +321,7 @@ static struct tegra_clk_init_table init_table[] = { {TEGRA124_CLK_PLL_P_OUT2, TEGRA124_CLK_CLK_MAX, 48000000, 1}, {TEGRA124_CLK_PLL_P_OUT3, TEGRA124_CLK_CLK_MAX, 102000000, 1}, {TEGRA124_CLK_PLL_P_OUT4, TEGRA124_CLK_CLK_MAX, 204000000, 1}, - {TEGRA124_CLK_MSELECT, TEGRA124_CLK_PLL_P, 204000000, 1}, + {TEGRA124_CLK_MSELECT, TEGRA124_CLK_PLL_P, 102000000, 1}, {TEGRA124_CLK_UARTA, TEGRA124_CLK_PLL_P, 0, 1}, {TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 0, 1}, {TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 0, 1}, diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 9997ab9666..7210053e96 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -351,7 +351,7 @@ static struct tegra_clk_init_table init_table[] = { {TEGRA30_CLK_PLL_P_OUT2, TEGRA30_CLK_CLK_MAX, 48000000, 1}, {TEGRA30_CLK_PLL_P_OUT3, TEGRA30_CLK_CLK_MAX, 102000000, 1}, {TEGRA30_CLK_PLL_P_OUT4, TEGRA30_CLK_CLK_MAX, 204000000, 1}, - {TEGRA30_CLK_MSELECT, TEGRA30_CLK_PLL_P, 204000000, 1}, + {TEGRA30_CLK_MSELECT, TEGRA30_CLK_PLL_P, 102000000, 1}, {TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 0, 1}, {TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 0, 1}, {TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 0, 1}, |