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| author | Lucas Stach <l.stach@pengutronix.de> | 2014-10-04 19:40:17 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-10-08 08:39:01 +0200 |
| commit | 72f493e3e607a43ea856fcb9ca3d73f397228622 (patch) | |
| tree | cb80e1df43fd92d67ba41e39030ec0e3e1589ea3 /drivers/clk | |
| parent | aa2e6ca831f4f02e133de0c5212a2773a62bb1d5 (diff) | |
| download | barebox-72f493e3e607a43ea856fcb9ca3d73f397228622.tar.gz barebox-72f493e3e607a43ea856fcb9ca3d73f397228622.tar.xz | |
clk: tegra30: add PCIe clocks
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra30.c | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index ed6d73625c..9997ab9666 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -130,6 +130,13 @@ static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { { 0, 0, 0, 0, 0, 0 }, }; +static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { + /* PLLE special case: use cpcon field to store cml divider value */ + { 12000000, 100000000, 150, 1, 18, 11}, + { 216000000, 100000000, 200, 18, 24, 13}, + { 0, 0, 0, 0, 0, 0 }, +}; + /* PLL parameters */ static struct tegra_clk_pll_params pll_c_params = { .input_min = 2000000, @@ -201,6 +208,19 @@ static struct tegra_clk_pll_params pll_u_params = { .lock_delay = 1000, }; +static struct tegra_clk_pll_params pll_e_params = { + .input_min = 12000000, + .input_max = 216000000, + .cf_min = 12000000, + .cf_max = 12000000, + .vco_min = 1200000000, + .vco_max = 2400000000U, + .base_reg = CRC_PLLE_BASE, + .misc_reg = CRC_PLLE_MISC, + .lock_enable_bit_idx = CRC_PLLE_MISC_LOCK_ENABLE, + .lock_delay = 300, +}; + static void tegra30_pll_init(void) { /* PLLC */ @@ -251,6 +271,11 @@ static void tegra30_pll_init(void) clks[TEGRA30_CLK_PLL_U] = tegra_clk_register_pll("pll_u", "pll_ref", car_base, 0, 0, &pll_u_params, TEGRA_PLLU | TEGRA_PLL_HAS_CPCON, pll_u_freq_table); + + /* PLLE */ + clks[TEGRA30_CLK_PLL_E] = tegra_clk_register_plle("pll_e", "pll_ref", + car_base, 0, 100000000, &pll_e_params, + TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK, pll_e_freq_table); } static const char *mux_pllpcm_clkm[] = {"pll_p", "pll_c", "pll_m", "clk_m"}; @@ -278,6 +303,12 @@ static void tegra30_periph_init(void) mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base, CRC_CLK_SOURCE_UARTE, TEGRA30_CLK_UARTE, TEGRA_PERIPH_ON_APB); + clks[TEGRA30_CLK_PCIE] = clk_gate("pcie", "clk_m", + car_base + CRC_CLK_OUT_ENB_U, 6, 0, 0); + clks[TEGRA30_CLK_AFI] = clk_gate("afi", "clk_m", + car_base + CRC_CLK_OUT_ENB_U, 8, 0, 0); + clks[TEGRA30_CLK_CML0] = clk_gate("cml0", "pll_e", + car_base + CRC_PLLE_AUX, 0, 0, 0); /* peripheral clocks with a divider */ clks[TEGRA30_CLK_MSELECT] = tegra_clk_register_periph("mselect", |