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author | Philipp Zabel <p.zabel@pengutronix.de> | 2019-07-17 19:06:02 +0200 |
---|---|---|
committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-08-05 12:21:00 +0200 |
commit | 24a3f5d69af9e7193ad1aa0cb02bf7a0ff369341 (patch) | |
tree | d1df020bcb6ddadabbfbde2906e6ed75ba08b597 /drivers/clk | |
parent | 98b1b9646c1958b9345508d80a47184316c6bac9 (diff) | |
download | barebox-24a3f5d69af9e7193ad1aa0cb02bf7a0ff369341.tar.gz barebox-24a3f5d69af9e7193ad1aa0cb02bf7a0ff369341.tar.xz |
clk: imx6: Make the LDB_DI0 and LDB_DI1 clocks read-only
Based on Kernel commit 03d576f202 ("clk: imx6: Make the LDB_DI0 and LDB_DI1 clocks read-only"):
| Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk
| tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to
| enter the ldb_di_ipu_div divider. If the divider gets locked up, no
| ldb_di[x]_clk is generated, and the LVDS display will hang when the
| ipu_di_clk is sourced from ldb_di_clk.
|
| To fix the problem, both the new and current parent of the ldb_di_clk
| should be disabled before the switch. As this can not be guaranteed by
| the clock framework during runtime, make the ldb_di[x]_sel muxes read-only.
| A workaround to set the muxes once during boot could be added to the
| kernel or bootloader.
|
| Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
| Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
| Signed-off-by: Shawn Guo <shawnguo@kernel.org>
[afa: reviewed for barebox]
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com>
[afa: ported from Linux kernel commit 03d576f202]
[afa: added exception for i.MX6QP, see kernel commit f4a0a6c309]
[afa: added cpu_has_err009219 helper function]
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/clk')
-rw-r--r-- | drivers/clk/imx/clk-imx6.c | 17 | ||||
-rw-r--r-- | drivers/clk/imx/clk.h | 8 |
2 files changed, 23 insertions, 2 deletions
diff --git a/drivers/clk/imx/clk-imx6.c b/drivers/clk/imx/clk-imx6.c index 6f19535be7..61819ff974 100644 --- a/drivers/clk/imx/clk-imx6.c +++ b/drivers/clk/imx/clk-imx6.c @@ -64,6 +64,13 @@ static inline int cpu_mx6_is_plus(void) return cpu_mx6_is_mx6qp() || cpu_mx6_is_mx6dp(); } +/* i.MX6 Quad/Dual/DualLite/Solo are all affected */ +static inline int cpu_mx6_has_err009219(void) +{ + return cpu_mx6_is_mx6d() || cpu_mx6_is_mx6q() || + cpu_mx6_is_mx6dl() || cpu_mx6_is_mx6s(); +} + static const char *step_sels[] = { "osc", "pll2_pfd2_396m", @@ -316,8 +323,14 @@ static void imx6_add_video_clks(void __iomem *anab, void __iomem *cb) imx6q_mmdc_ch1_mask_handshake(cb); - clks[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_p("ldb_di0_sel", cb + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels)); - clks[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_p("ldb_di1_sel", cb + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels)); + if (cpu_mx6_has_err009219()) { + clks[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_ldb("ldb_di0_sel", cb + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels)); + clks[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_ldb("ldb_di1_sel", cb + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels)); + } else { + clks[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_p("ldb_di0_sel", cb + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels)); + clks[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_p("ldb_di1_sel", cb + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels)); + } + clks[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_mux_p("ipu1_di0_pre_sel", cb + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); clks[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_mux_p("ipu1_di1_pre_sel", cb + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); clks[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_mux_p("ipu2_di0_pre_sel", cb + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 875c76a8b3..04286f03f7 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -39,6 +39,14 @@ static inline struct clk *imx_clk_divider_table(const char *name, width, table, 0); } +static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg, + u8 shift, u8 width, const char **parents, int num_parents) +{ + return clk_mux(name, CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg, + shift, width, parents, num_parents, CLK_MUX_READ_ONLY); +} + + static inline struct clk *imx_clk_fixed_factor(const char *name, const char *parent, unsigned int mult, unsigned int div) { |