mtd: gpmi-nand: Make sure clock is disabled during rate change

On i.MX6 GPMI Nand controller the clock must be disabled during
a rate change. Otherwise glitches on the clock line may occur
which result in errors like:

MXS NAND: Error sending command
MXS NAND: DMA read error

There were previous attempts to fix this. One is in:

54961378f0 imx6: clk: Gate off ENFC clock before setting clock rate

This patch added a clk_disable() right before the rate change. Since
a clk_disable() on a disabled clk is a no-op, the patch added a
clk_enable() to the i.MX6 clk driver in the hope that the clk is
enabled in the nand driver probe and the clk_disable() really takes
place.

This patch doesn't work. First of all it enabled the enfc_podf clk
which was not the one that was actually disabled in the nand driver,
resulting in the nand drivers call to clk_disable() still being a
no-op. Then this patch also only works only on the classic i.MX6 which
was the only one supported at that time, but not on the i.MX6UL, i.MX6SX
and i.MX6SL which have a separate clk driver.

Instead of adding more quirks to the other i.MX6 clk drivers, fix this
in the GPMI driver. We no longer call clk_disable() on a disabled clk,
but instead do a clk_enable() first which makes sure the hardware state
is synchronized to the usage count and the following clk_disable()
is really effective. At the same time we can (and actually must) remove
the quirk in the i.MX6 clk driver.

Also add clk_disable()/clk_enable() around another rate change in the
GPMI driver.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

1 files changed, 0 insertions, 1 deletions

diff --git a/drivers/clk/imx/clk-imx6.c b/drivers/clk/imx/clk-imx6.c
index 8c3bb46a48..35b995dae2 100644
--- a/drivers/clk/imx/clk-imx6.c
+++ b/drivers/clk/imx/clk-imx6.c
@@ -527,7 +527,6 @@ static int imx6_ccm_probe(struct device_d *dev)
 	clk_enable(clks[IMX6QDL_CLK_MMDC_CH0_AXI_PODF]);
 	clk_enable(clks[IMX6QDL_CLK_PLL6_ENET]);
 	clk_enable(clks[IMX6QDL_CLK_SATA_REF_100M]);
-	clk_enable(clks[IMX6QDL_CLK_ENFC_PODF]);
 
 	clk_set_parent(clks[IMX6QDL_CLK_LVDS1_SEL], clks[IMX6QDL_CLK_SATA_REF_100M]);