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| author | Lucas Stach <l.stach@pengutronix.de> | 2018-12-10 15:32:39 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-12-13 07:47:39 +0100 |
| commit | a926e6866959409d315ed4d1afe4b1f844c15e69 (patch) | |
| tree | 368858a1d21fb976c43eb3aa713361a99f17a27d /drivers/clk | |
| parent | d71cbc669495051c00f36cccfa9197451530f264 (diff) | |
| download | barebox-a926e6866959409d315ed4d1afe4b1f844c15e69.tar.gz barebox-a926e6866959409d315ed4d1afe4b1f844c15e69.tar.xz | |
clk: imx5: add di_pred
This was missing, so the default external DI clock source on i.MX51 was
missing. Also set the divider to a division ratio of 1 initially, to avoid
complicating the logic in the IPU driver further.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/imx/clk-imx5.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk-imx5.c b/drivers/clk/imx/clk-imx5.c index f59a41b001..69ac2f5e3e 100644 --- a/drivers/clk/imx/clk-imx5.c +++ b/drivers/clk/imx/clk-imx5.c @@ -271,6 +271,7 @@ static void mx5_clocks_mx51_mx53_init(void __iomem *base) clks[IMX5_CLK_USBOH3_PODF] = imx_clk_divider("usboh3_podf", "usboh3_pred", base + CCM_CSCDR1, 6, 2); clks[IMX5_CLK_USB_PHY_PRED] = imx_clk_divider("usb_phy_pred", "pll3_sw", base + CCM_CDCDR, 3, 3); clks[IMX5_CLK_USB_PHY_PODF] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", base + CCM_CDCDR, 0, 3); + clks[IMX5_CLK_DI_PRED] = imx_clk_divider_np("di_pred", "pll3_sw", base + CCM_CDCDR, 6, 3); clks[IMX5_CLK_USB_PHY_SEL] = imx_clk_mux("usb_phy_sel", base + CCM_CSCMR1, 26, 1, usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str)); } @@ -362,6 +363,8 @@ static void mx51_clocks_ipu_init(void __iomem *regs) mx5_clocks_ipu_init(regs); + clk_set_rate(clks[IMX5_CLK_DI_PRED], clk_get_rate(clks[IMX5_CLK_PLL3_SW])); + clkdev_add_physbase(clks[IMX5_CLK_IPU_SEL], MX51_IPU_BASE_ADDR, "bus"); clkdev_add_physbase(clks[IMX5_CLK_IPU_DI0_SEL], MX51_IPU_BASE_ADDR, "di0"); clkdev_add_physbase(clks[IMX5_CLK_IPU_DI1_SEL], MX51_IPU_BASE_ADDR, "di1"); |