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| author | Marcin Niestroj <m.niestroj@grinn-global.com> | 2018-09-03 13:23:53 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-09-04 10:03:49 +0200 |
| commit | 6907e24ef4c21f2dbe370657ac4a9b2741777cb3 (patch) | |
| tree | 5c953d40e7a7f30e6ce4e6c210b1d7cd3a5c92a6 /drivers/crypto | |
| parent | 947e727947748885e9b918f743388f829758a657 (diff) | |
| download | barebox-6907e24ef4c21f2dbe370657ac4a9b2741777cb3.tar.gz barebox-6907e24ef4c21f2dbe370657ac4a9b2741777cb3.tar.xz | |
crypto: caam - fix writing to JQCR_MS when using service interface
Pick commit 9f587fa29f7e8ed6b8885cff51a51ace3ad85152 from Linux
upstream.
crypto: caam - fix writing to JQCR_MS when using service interface
Most significant part of JQCR (Job Queue Control Register) contains
bits that control endianness: ILE - Immediate Little Endian,
DWS - Double Word Swap.
The bits are automatically set by the Job Queue Controller HW.
Unfortunately these bits are cleared in SW when submitting descriptors
via the register-based service interface.
>From LS1021A:
JQCR_MS = 08080100 - before writing: ILE | DWS | SRC (JR0)
JQCR_MS = 30000100 - after writing: WHL | FOUR | SRC (JR0)
This would cause problems on little endian caam for descriptors
containing immediata data or double-word pointers.
Currently there is no problem since the only descriptors ran through
this interface are the ones that (un)instantiate RNG.
Signed-off-by: Horia Geant? <horia.geanta@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/crypto')
| -rw-r--r-- | drivers/crypto/caam/ctrl.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c index eafff8ef0a..8ce9a859e1 100644 --- a/drivers/crypto/caam/ctrl.c +++ b/drivers/crypto/caam/ctrl.c @@ -117,7 +117,7 @@ static inline int run_descriptor_deco0(struct device_d *ctrldev, u32 *desc, flags |= DECO_JQCR_FOUR; /* Instruct the DECO to execute it */ - writel(flags, &deco->jr_ctl_hi); + setbits32(&deco->jr_ctl_hi, flags); start = get_time_ns(); while ((deco_dbg_reg = readl(&deco->desc_dbg)) & |