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| author | Lucas Stach <l.stach@pengutronix.de> | 2020-11-05 15:10:15 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2020-11-09 11:23:12 +0100 |
| commit | cca126664350433891bf63c33db26ef9f0014ea1 (patch) | |
| tree | 097d863da201f55a8df7e3f7ba52a8fab77ac3d8 /drivers/ddr/imx8m/ddrphy_train.c | |
| parent | 61682b59363fca0fbf51d37ece46ec6d47ea35d4 (diff) | |
| download | barebox-cca126664350433891bf63c33db26ef9f0014ea1.tar.gz barebox-cca126664350433891bf63c33db26ef9f0014ea1.tar.xz | |
ddr: imx8m: add workaround for DDRPHY rank to rank issue
This is a port of upstream U-Boot commit b335966958a9. Sadly there is no
more information to be found about the issue. The currently available
errata documents don't mention this issue at all and the U-Boot commit
doesn't tell much either, however this commit has been pointed out by
NXP engineers as a solution to reports of board instabilities.
| drivers: ddr: imx Workaround for i.MX8M DDRPHY rank to rank issue
|
| Add logic to automatically update umctl2's setting based
| on phy training CDD value for rank to rank space issue
|
| Acked-by: Ye Li <ye.li@nxp.com>
| Signed-off-by: Oliver Chen <Oliver.Chen@nxp.com>
| Signed-off-by: Jacky Bai <ping.bai@nxp.com>
| Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Sascha Hauer <s.hauer@pengutronix.de> (on i.MX8MP)
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/ddr/imx8m/ddrphy_train.c')
| -rw-r--r-- | drivers/ddr/imx8m/ddrphy_train.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/ddr/imx8m/ddrphy_train.c b/drivers/ddr/imx8m/ddrphy_train.c index ca0bb2f57b..9280c853aa 100644 --- a/drivers/ddr/imx8m/ddrphy_train.c +++ b/drivers/ddr/imx8m/ddrphy_train.c @@ -93,7 +93,12 @@ int ddr_cfg_phy(struct dram_timing_info *dram_timing) /* Read the Message Block results */ dwc_ddrphy_apb_wr(0xd0000, 0x0); + ddrphy_init_read_msg_block(fsp_msg->fw_type); + + if (fsp_msg->fw_type != FW_2D_IMAGE) + get_trained_CDD(i); + dwc_ddrphy_apb_wr(0xd0000, 0x1); fsp_msg++; |