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author | Sascha Hauer <s.hauer@pengutronix.de> | 2011-07-04 17:18:46 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2011-07-25 11:14:01 +0200 |
commit | d8f171b96e7f7b466f8b2a061380d4958a492eb9 (patch) | |
tree | e2cbdd60572862b9dc8e72ac960858e4c42fae45 /drivers/mci/imx-esdhc.c | |
parent | 522af7074a333508d8b73c25abd1d051d8672e5c (diff) | |
download | barebox-d8f171b96e7f7b466f8b2a061380d4958a492eb9.tar.gz barebox-d8f171b96e7f7b466f8b2a061380d4958a492eb9.tar.xz |
MCI imx-esdhc: Fix multiblock transfers on i.MX53
In the Kernel this bug is described like this:
> The CMDTYPE of the CMD register (offset 0xE) should be set to
> "11" when the STOP CMD12 is issued on imx53 to abort one
> open ended multi-blk IO. Otherwise the TC INT wouldn't
> be generated.
> In exact block transfer, the controller doesn't complete the
> operations automatically as required at the end of the
> transfer and remains on hold if the abort command is not sent.
> As a result, the TC flag is not asserted and SW received timeout
> exeception. Bit1 of Vendor Spec registor is used to fix it.
We do not use exact block transfers in barebox, so we only need
the first part of this fix.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/mci/imx-esdhc.c')
-rw-r--r-- | drivers/mci/imx-esdhc.c | 21 |
1 files changed, 13 insertions, 8 deletions
diff --git a/drivers/mci/imx-esdhc.c b/drivers/mci/imx-esdhc.c index 5c2a2f40b1..4cc2423424 100644 --- a/drivers/mci/imx-esdhc.c +++ b/drivers/mci/imx-esdhc.c @@ -35,6 +35,7 @@ #include <asm/io.h> #include <asm/mmu.h> #include <mach/clock.h> +#include <mach/generic.h> #include "imx-esdhc.h" @@ -75,6 +76,8 @@ struct fsl_esdhc_host { #define to_fsl_esdhc(mci) container_of(mci, struct fsl_esdhc_host, mci) +#define SDHCI_CMD_ABORTCMD (0xC0 << 16) + /* Return the XFERTYP flags for a given command and data packet */ u32 esdhc_xfertyp(struct mci_cmd *cmd, struct mci_data *data) { @@ -104,6 +107,8 @@ u32 esdhc_xfertyp(struct mci_cmd *cmd, struct mci_data *data) xfertyp |= XFERTYP_RSPTYP_48_BUSY; else if (cmd->resp_type & MMC_RSP_PRESENT) xfertyp |= XFERTYP_RSPTYP_48; + if (cpu_is_mx53() && cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) + xfertyp |= SDHCI_CMD_ABORTCMD; return XFERTYP_CMD(cmd->cmdidx) | xfertyp; } @@ -233,14 +238,6 @@ esdhc_send_cmd(struct mci_host *mci, struct mci_cmd *cmd, struct mci_data *data) esdhc_write32(®s->irqstat, -1); - /* Wait for the bus to be idle */ - while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || - (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) - ; - - while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) - ; - /* Wait at least 8 SD clock cycles before the next command */ /* * Note: This is way more than 8 cycles, but 1ms seems to @@ -324,6 +321,14 @@ esdhc_send_cmd(struct mci_host *mci, struct mci_cmd *cmd, struct mci_data *data) esdhc_write32(®s->irqstat, -1); + /* Wait for the bus to be idle */ + while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || + (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) + ; + + while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) + ; + return 0; } |