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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2019-01-30 16:34:05 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-02-07 08:56:07 +0100 |
| commit | 3354adee3920de4a5b2974db08f843180d0e5884 (patch) | |
| tree | afec767e0641df10a8a4f2fcd544be3ff0372b10 /drivers/mci | |
| parent | fb174c210cf5a8bb099893043d659300ff4e39d9 (diff) | |
| download | barebox-3354adee3920de4a5b2974db08f843180d0e5884.tar.gz barebox-3354adee3920de4a5b2974db08f843180d0e5884.tar.xz | |
mci: imx-esdhc: Add bigendian register access support
Layerscape will need bigendian io accessors. Add support for them.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/mci')
| -rw-r--r-- | drivers/mci/imx-esdhc.c | 21 |
1 files changed, 15 insertions, 6 deletions
diff --git a/drivers/mci/imx-esdhc.c b/drivers/mci/imx-esdhc.c index dfe334f14d..2bf7687d7b 100644 --- a/drivers/mci/imx-esdhc.c +++ b/drivers/mci/imx-esdhc.c @@ -67,6 +67,9 @@ #define ESDHC_FLAG_STD_TUNING BIT(5) /* The IP has SDHCI_CAPABILITIES_1 register */ #define ESDHC_FLAG_HAVE_CAP1 BIT(6) +/* Need to access registers in bigendian mode */ +#define ESDHC_FLAG_BIGENDIAN BIT(7) + /* * The IP has errata ERR004536 * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow, @@ -108,13 +111,19 @@ static inline int esdhc_is_usdhc(struct fsl_esdhc_host *data) static inline u32 esdhc_read32(struct fsl_esdhc_host *host, unsigned int reg) { - return readl(host->regs + reg); + if (host->socdata->flags & ESDHC_FLAG_BIGENDIAN) + return in_be32(host->regs + reg); + else + return readl(host->regs + reg); } static inline void esdhc_write32(struct fsl_esdhc_host *host, unsigned int reg, u32 val) { - writel(val, host->regs + reg); + if (host->socdata->flags & ESDHC_FLAG_BIGENDIAN) + out_be32(host->regs + reg, val); + else + writel(val, host->regs + reg); } static inline void esdhc_clrsetbits32(struct fsl_esdhc_host *host, unsigned int reg, @@ -583,7 +592,6 @@ static int esdhc_reset(struct fsl_esdhc_host *host) static int esdhc_init(struct mci_host *mci, struct device_d *dev) { struct fsl_esdhc_host *host = to_fsl_esdhc(mci); - void __iomem *regs = host->regs; int ret; ret = esdhc_reset(host); @@ -599,9 +607,10 @@ static int esdhc_init(struct mci_host *mci, struct device_d *dev) /* Set the initial clock speed */ set_sysctl(mci, 400000); - writel(IRQSTATEN_CC | IRQSTATEN_TC | IRQSTATEN_CINT | IRQSTATEN_CTOE | - IRQSTATEN_CCE | IRQSTATEN_CEBE | IRQSTATEN_CIE | IRQSTATEN_DTOE | - IRQSTATEN_DCE | IRQSTATEN_DEBE | IRQSTATEN_DINT, regs + SDHCI_INT_ENABLE); + esdhc_write32(host, SDHCI_INT_ENABLE, IRQSTATEN_CC | IRQSTATEN_TC | + IRQSTATEN_CINT | IRQSTATEN_CTOE | IRQSTATEN_CCE | + IRQSTATEN_CEBE | IRQSTATEN_CIE | IRQSTATEN_DTOE | + IRQSTATEN_DCE | IRQSTATEN_DEBE | IRQSTATEN_DINT); /* Put the PROCTL reg back to the default */ esdhc_write32(host, SDHCI_HOST_CONTROL__POWER_CONTROL__BLOCK_GAP_CONTROL, |