mtd: nand: update to v3.11-rc1

This updates the NAND stuff to Linux-3.11-rc1. It is synchronized
as best as we can get:

- locks removed
- The splitting in different files we had to better support different
  features has been dropped. Instead this is now done mostly with the
  use of __maybe_unused

Some barebox adjustments are forward ported, like:

- Allow partial page writes
- Optionally allow to erase bad blocks
- check for all_ff before writing a page

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

1 files changed, 130 insertions, 136 deletions

diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index 4f8fb021a9..52b0da5927 100644
--- a/drivers/mtd/nand/nand_ids.c
+++ b/drivers/mtd/nand/nand_ids.c
@@ -3,184 +3,178 @@
  *
  *  Copyright (C) 2002 Thomas Gleixner (tglx@linutronix.de)
  *
- * $Id: nand_ids.c,v 1.16 2005/11/07 11:14:31 gleixner Exp $
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  *
  */
 #include <common.h>
+#include <sizes.h>
 #include <linux/mtd/nand.h>
 
 #ifdef CONFIG_NAND_INFO
-#define __NANDSTR(str)	str
+#define __STR(str) str
 #else
-#define __NANDSTR(str)	""
-#endif
-
-/*
-*	Chip ID list
-*
-*	Name. ID code, pagesize, chipsize in MegaByte, eraseblock size,
-*	options
-*
-*	Pagesize; 0, 256, 512
-*	0	get this information from the extended chip ID
-+	256	256 Byte page size
-*	512	512 Byte page size
-*/
-struct nand_flash_dev nand_flash_ids[] = {
-
-#ifdef CONFIG_MTD_NAND_MUSEUM_IDS
-	{__NANDSTR("NAND 1MiB 5V 8-bit"),	0x6e, 256, 1, 0x1000, 0},
-	{__NANDSTR("NAND 2MiB 5V 8-bit"),	0x64, 256, 2, 0x1000, 0},
-	{__NANDSTR("NAND 4MiB 5V 8-bit"),	0x6b, 512, 4, 0x2000, 0},
-	{__NANDSTR("NAND 1MiB 3,3V 8-bit"),	0xe8, 256, 1, 0x1000, 0},
-	{__NANDSTR("NAND 1MiB 3,3V 8-bit"),	0xec, 256, 1, 0x1000, 0},
-	{__NANDSTR("NAND 2MiB 3,3V 8-bit"),	0xea, 256, 2, 0x1000, 0},
-	{__NANDSTR("NAND 4MiB 3,3V 8-bit"),	0xd5, 512, 4, 0x2000, 0},
-	{__NANDSTR("NAND 4MiB 3,3V 8-bit"),	0xe3, 512, 4, 0x2000, 0},
-	{__NANDSTR("NAND 4MiB 3,3V 8-bit"),	0xe5, 512, 4, 0x2000, 0},
-	{__NANDSTR("NAND 8MiB 3,3V 8-bit"),	0xd6, 512, 8, 0x2000, 0},
-
-	{__NANDSTR("NAND 8MiB 1,8V 8-bit"),	0x39, 512, 8, 0x2000, 0},
-	{__NANDSTR("NAND 8MiB 3,3V 8-bit"),	0xe6, 512, 8, 0x2000, 0},
-	{__NANDSTR("NAND 8MiB 1,8V 16-bit"),	0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
-	{__NANDSTR("NAND 8MiB 3,3V 16-bit"),	0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
+#define __STR(str) ""
 #endif
 
-	{__NANDSTR("NAND 16MiB 1,8V 8-bit"),	0x33, 512, 16, 0x4000, 0},
-	{__NANDSTR("NAND 16MiB 3,3V 8-bit"),	0x73, 512, 16, 0x4000, 0},
-	{__NANDSTR("NAND 16MiB 1,8V 16-bit"),	0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
-	{__NANDSTR("NAND 16MiB 3,3V 16-bit"),	0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
-
-	{__NANDSTR("NAND 32MiB 1,8V 8-bit"),	0x35, 512, 32, 0x4000, 0},
-	{__NANDSTR("NAND 32MiB 3,3V 8-bit"),	0x75, 512, 32, 0x4000, 0},
-	{__NANDSTR("NAND 32MiB 1,8V 16-bit"),	0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
-	{__NANDSTR("NAND 32MiB 3,3V 16-bit"),	0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
-
-	{__NANDSTR("NAND 64MiB 1,8V 8-bit"),	0x36, 512, 64, 0x4000, 0},
-	{__NANDSTR("NAND 64MiB 3,3V 8-bit"),	0x76, 512, 64, 0x4000, 0},
-	{__NANDSTR("NAND 64MiB 1,8V 16-bit"),	0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
-	{__NANDSTR("NAND 64MiB 3,3V 16-bit"),	0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
+#define LP_OPTIONS NAND_SAMSUNG_LP_OPTIONS
+#define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16)
 
-	{__NANDSTR("NAND 128MiB 1,8V 8-bit"),	0x78, 512, 128, 0x4000, 0},
-	{__NANDSTR("NAND 128MiB 1,8V 8-bit"),	0x39, 512, 128, 0x4000, 0},
-	{__NANDSTR("NAND 128MiB 3,3V 8-bit"),	0x79, 512, 128, 0x4000, 0},
-	{__NANDSTR("NAND 128MiB 1,8V 16-bit"),	0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
-	{__NANDSTR("NAND 128MiB 1,8V 16-bit"),	0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
-	{__NANDSTR("NAND 128MiB 3,3V 16-bit"),	0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
-	{__NANDSTR("NAND 128MiB 3,3V 16-bit"),	0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
+#define SP_OPTIONS NAND_NEED_READRDY
+#define SP_OPTIONS16 (SP_OPTIONS | NAND_BUSWIDTH_16)
 
-	{__NANDSTR("NAND 256MiB 3,3V 8-bit"),	0x71, 512, 256, 0x4000, 0},
+/*
+ * The chip ID list:
+ *    name, device ID, page size, chip size in MiB, eraseblock size, options
+ *
+ * If page size and eraseblock size are 0, the sizes are taken from the
+ * extended chip ID.
+ */
+struct nand_flash_dev nand_flash_ids[] = {
+	/*
+	 * Some incompatible NAND chips share device ID's and so must be
+	 * listed by full ID. We list them first so that we can easily identify
+	 * the most specific match.
+	 */
+	{__STR("TC58NVG2S0F 4G 3.3V 8-bit"),
+		{ .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} },
+		  SZ_4K, SZ_512, SZ_256K, 0, 8, 224},
+	{__STR("TC58NVG3S0F 8G 3.3V 8-bit"),
+		{ .id = {0x98, 0xd3, 0x90, 0x26, 0x76, 0x15, 0x02, 0x08} },
+		  SZ_4K, SZ_1K, SZ_256K, 0, 8, 232},
+	{__STR("TC58NVG5D2 32G 3.3V 8-bit"),
+		{ .id = {0x98, 0xd7, 0x94, 0x32, 0x76, 0x56, 0x09, 0x00} },
+		  SZ_8K, SZ_4K, SZ_1M, 0, 8, 640},
+	{__STR("TC58NVG6D2 64G 3.3V 8-bit"),
+		{ .id = {0x98, 0xde, 0x94, 0x82, 0x76, 0x56, 0x04, 0x20} },
+		  SZ_8K, SZ_8K, SZ_2M, 0, 8, 640},
+
+	LEGACY_ID_NAND(__STR("NAND 4MiB 5V 8-bit"),   0x6B, 4, SZ_8K, SP_OPTIONS),
+	LEGACY_ID_NAND(__STR("NAND 4MiB 3,3V 8-bit"), 0xE3, 4, SZ_8K, SP_OPTIONS),
+	LEGACY_ID_NAND(__STR("NAND 4MiB 3,3V 8-bit"), 0xE5, 4, SZ_8K, SP_OPTIONS),
+	LEGACY_ID_NAND(__STR("NAND 8MiB 3,3V 8-bit"), 0xD6, 8, SZ_8K, SP_OPTIONS),
+	LEGACY_ID_NAND(__STR("NAND 8MiB 3,3V 8-bit"), 0xE6, 8, SZ_8K, SP_OPTIONS),
+
+	LEGACY_ID_NAND(__STR("NAND 16MiB 1,8V 8-bit"),  0x33, 16, SZ_16K, SP_OPTIONS),
+	LEGACY_ID_NAND(__STR("NAND 16MiB 3,3V 8-bit"),  0x73, 16, SZ_16K, SP_OPTIONS),
+	LEGACY_ID_NAND(__STR("NAND 16MiB 1,8V 16-bit"), 0x43, 16, SZ_16K, SP_OPTIONS16),
+	LEGACY_ID_NAND(__STR("NAND 16MiB 3,3V 16-bit"), 0x53, 16, SZ_16K, SP_OPTIONS16),
+
+	LEGACY_ID_NAND(__STR("NAND 32MiB 1,8V 8-bit"),  0x35, 32, SZ_16K, SP_OPTIONS),
+	LEGACY_ID_NAND(__STR("NAND 32MiB 3,3V 8-bit"),  0x75, 32, SZ_16K, SP_OPTIONS),
+	LEGACY_ID_NAND(__STR("NAND 32MiB 1,8V 16-bit"), 0x45, 32, SZ_16K, SP_OPTIONS16),
+	LEGACY_ID_NAND(__STR("NAND 32MiB 3,3V 16-bit"), 0x55, 32, SZ_16K, SP_OPTIONS16),
+
+	LEGACY_ID_NAND(__STR("NAND 64MiB 1,8V 8-bit"),  0x36, 64, SZ_16K, SP_OPTIONS),
+	LEGACY_ID_NAND(__STR("NAND 64MiB 3,3V 8-bit"),  0x76, 64, SZ_16K, SP_OPTIONS),
+	LEGACY_ID_NAND(__STR("NAND 64MiB 1,8V 16-bit"), 0x46, 64, SZ_16K, SP_OPTIONS16),
+	LEGACY_ID_NAND(__STR("NAND 64MiB 3,3V 16-bit"), 0x56, 64, SZ_16K, SP_OPTIONS16),
+
+	LEGACY_ID_NAND(__STR("NAND 128MiB 1,8V 8-bit"),  0x78, 128, SZ_16K, SP_OPTIONS),
+	LEGACY_ID_NAND(__STR("NAND 128MiB 1,8V 8-bit"),  0x39, 128, SZ_16K, SP_OPTIONS),
+	LEGACY_ID_NAND(__STR("NAND 128MiB 3,3V 8-bit"),  0x79, 128, SZ_16K, SP_OPTIONS),
+	LEGACY_ID_NAND(__STR("NAND 128MiB 1,8V 16-bit"), 0x72, 128, SZ_16K, SP_OPTIONS16),
+	LEGACY_ID_NAND(__STR("NAND 128MiB 1,8V 16-bit"), 0x49, 128, SZ_16K, SP_OPTIONS16),
+	LEGACY_ID_NAND(__STR("NAND 128MiB 3,3V 16-bit"), 0x74, 128, SZ_16K, SP_OPTIONS16),
+	LEGACY_ID_NAND(__STR("NAND 128MiB 3,3V 16-bit"), 0x59, 128, SZ_16K, SP_OPTIONS16),
+
+	LEGACY_ID_NAND(__STR("NAND 256MiB 3,3V 8-bit"), 0x71, 256, SZ_16K, SP_OPTIONS),
 
 	/*
-	 * These are the new chips with large page size. The pagesize and the
-	 * erasesize is determined from the extended id bytes
+	 * These are the new chips with large page size. Their page size and
+	 * eraseblock size are determined from the extended ID bytes.
 	 */
-#define LP_OPTIONS (NAND_SAMSUNG_LP_OPTIONS | NAND_NO_READRDY | NAND_NO_AUTOINCR)
-#define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16)
 
-	/*512 Megabit */
-	{__NANDSTR("NAND 64MiB 1,8V 8-bit"),	0xA2, 0,  64, 0, LP_OPTIONS},
-	{__NANDSTR("NAND 64MiB 3,3V 8-bit"),	0xF2, 0,  64, 0, LP_OPTIONS},
-	{__NANDSTR("NAND 64MiB 1,8V 16-bit"),	0xB2, 0,  64, 0, LP_OPTIONS16},
-	{__NANDSTR("NAND 64MiB 3,3V 16-bit"),	0xC2, 0,  64, 0, LP_OPTIONS16},
+	/* 512 Megabit */
+	EXTENDED_ID_NAND(__STR("NAND 64MiB 1,8V 8-bit"),  0xA2,  64, LP_OPTIONS),
+	EXTENDED_ID_NAND(__STR("NAND 64MiB 1,8V 8-bit"),  0xA0,  64, LP_OPTIONS),
+	EXTENDED_ID_NAND(__STR("NAND 64MiB 3,3V 8-bit"),  0xF2,  64, LP_OPTIONS),
+	EXTENDED_ID_NAND(__STR("NAND 64MiB 3,3V 8-bit"),  0xD0,  64, LP_OPTIONS),
+	EXTENDED_ID_NAND(__STR("NAND 64MiB 3,3V 8-bit"),  0xF0,  64, LP_OPTIONS),
+	EXTENDED_ID_NAND(__STR("NAND 64MiB 1,8V 16-bit"), 0xB2,  64, LP_OPTIONS16),
+	EXTENDED_ID_NAND(__STR("NAND 64MiB 1,8V 16-bit"), 0xB0,  64, LP_OPTIONS16),
+	EXTENDED_ID_NAND(__STR("NAND 64MiB 3,3V 16-bit"), 0xC2,  64, LP_OPTIONS16),
+	EXTENDED_ID_NAND(__STR("NAND 64MiB 3,3V 16-bit"), 0xC0,  64, LP_OPTIONS16),
 
 	/* 1 Gigabit */
-	{__NANDSTR("NAND 128MiB 1,8V 8-bit"),	0xA1, 0, 128, 0, LP_OPTIONS},
-	{__NANDSTR("NAND 128MiB 3,3V 8-bit"),	0xF1, 0, 128, 0, LP_OPTIONS},
-	{__NANDSTR("NAND 128MiB 1,8V 16-bit"),	0xB1, 0, 128, 0, LP_OPTIONS16},
-	{__NANDSTR("NAND 128MiB 3,3V 16-bit"),	0xC1, 0, 128, 0, LP_OPTIONS16},
+	EXTENDED_ID_NAND(__STR("NAND 128MiB 1,8V 8-bit"),  0xA1, 128, LP_OPTIONS),
+	EXTENDED_ID_NAND(__STR("NAND 128MiB 3,3V 8-bit"),  0xF1, 128, LP_OPTIONS),
+	EXTENDED_ID_NAND(__STR("NAND 128MiB 3,3V 8-bit"),  0xD1, 128, LP_OPTIONS),
+	EXTENDED_ID_NAND(__STR("NAND 128MiB 1,8V 16-bit"), 0xB1, 128, LP_OPTIONS16),
+	EXTENDED_ID_NAND(__STR("NAND 128MiB 3,3V 16-bit"), 0xC1, 128, LP_OPTIONS16),
+	EXTENDED_ID_NAND(__STR("NAND 128MiB 1,8V 16-bit"), 0xAD, 128, LP_OPTIONS16),
 
 	/* 2 Gigabit */
-	{__NANDSTR("NAND 256MiB 1,8V 8-bit"),	0xAA, 0, 256, 0, LP_OPTIONS},
-	{__NANDSTR("NAND 256MiB 3,3V 8-bit"),	0xDA, 0, 256, 0, LP_OPTIONS},
-	{__NANDSTR("NAND 256MiB 1,8V 16-bit"),	0xBA, 0, 256, 0, LP_OPTIONS16},
-	{__NANDSTR("NAND 256MiB 3,3V 16-bit"),	0xCA, 0, 256, 0, LP_OPTIONS16},
+	EXTENDED_ID_NAND(__STR("NAND 256MiB 1,8V 8-bit"),  0xAA, 256, LP_OPTIONS),
+	EXTENDED_ID_NAND(__STR("NAND 256MiB 3,3V 8-bit"),  0xDA, 256, LP_OPTIONS),
+	EXTENDED_ID_NAND(__STR("NAND 256MiB 1,8V 16-bit"), 0xBA, 256, LP_OPTIONS16),
+	EXTENDED_ID_NAND(__STR("NAND 256MiB 3,3V 16-bit"), 0xCA, 256, LP_OPTIONS16),
 
 	/* 4 Gigabit */
-	{__NANDSTR("NAND 512MiB 1,8V 8-bit"),	0xAC, 0, 512, 0, LP_OPTIONS},
-	{__NANDSTR("NAND 512MiB 3,3V 8-bit"),	0xDC, 0, 512, 0, LP_OPTIONS},
-	{__NANDSTR("NAND 512MiB 1,8V 16-bit"),	0xBC, 0, 512, 0, LP_OPTIONS16},
-	{__NANDSTR("NAND 512MiB 3,3V 16-bit"),	0xCC, 0, 512, 0, LP_OPTIONS16},
+	EXTENDED_ID_NAND(__STR("NAND 512MiB 1,8V 8-bit"),  0xAC, 512, LP_OPTIONS),
+	EXTENDED_ID_NAND(__STR("NAND 512MiB 3,3V 8-bit"),  0xDC, 512, LP_OPTIONS),
+	EXTENDED_ID_NAND(__STR("NAND 512MiB 1,8V 16-bit"), 0xBC, 512, LP_OPTIONS16),
+	EXTENDED_ID_NAND(__STR("NAND 512MiB 3,3V 16-bit"), 0xCC, 512, LP_OPTIONS16),
 
 	/* 8 Gigabit */
-	{__NANDSTR("NAND 1GiB 1,8V 8-bit"),	0xA3, 0, 1024, 0, LP_OPTIONS},
-	{__NANDSTR("NAND 1GiB 3,3V 8-bit"),	0xD3, 0, 1024, 0, LP_OPTIONS},
-	{__NANDSTR("NAND 1GiB 1,8V 16-bit"),	0xB3, 0, 1024, 0, LP_OPTIONS16},
-	{__NANDSTR("NAND 1GiB 3,3V 16-bit"),	0xC3, 0, 1024, 0, LP_OPTIONS16},
+	EXTENDED_ID_NAND(__STR("NAND 1GiB 1,8V 8-bit"),  0xA3, 1024, LP_OPTIONS),
+	EXTENDED_ID_NAND(__STR("NAND 1GiB 3,3V 8-bit"),  0xD3, 1024, LP_OPTIONS),
+	EXTENDED_ID_NAND(__STR("NAND 1GiB 1,8V 16-bit"), 0xB3, 1024, LP_OPTIONS16),
+	EXTENDED_ID_NAND(__STR("NAND 1GiB 3,3V 16-bit"), 0xC3, 1024, LP_OPTIONS16),
 
 	/* 16 Gigabit */
-	{__NANDSTR("NAND 2GiB 1,8V 8-bit"),	0xA5, 0, 2048, 0, LP_OPTIONS},
-	{__NANDSTR("NAND 2GiB 3,3V 8-bit"),	0xD5, 0, 2048, 0, LP_OPTIONS},
-	{__NANDSTR("NAND 2GiB 1,8V 16-bit"),	0xB5, 0, 2048, 0, LP_OPTIONS16},
-	{__NANDSTR("NAND 2GiB 3,3V 16-bit"),	0xC5, 0, 2048, 0, LP_OPTIONS16},
+	EXTENDED_ID_NAND(__STR("NAND 2GiB 1,8V 8-bit"),  0xA5, 2048, LP_OPTIONS),
+	EXTENDED_ID_NAND(__STR("NAND 2GiB 3,3V 8-bit"),  0xD5, 2048, LP_OPTIONS),
+	EXTENDED_ID_NAND(__STR("NAND 2GiB 1,8V 16-bit"), 0xB5, 2048, LP_OPTIONS16),
+	EXTENDED_ID_NAND(__STR("NAND 2GiB 3,3V 16-bit"), 0xC5, 2048, LP_OPTIONS16),
 
 	/* 32 Gigabit */
-	{__NANDSTR("NAND 4GiB 1,8V 8-bit"),	0xA7, 0, 4096, 0, LP_OPTIONS},
-	{__NANDSTR("NAND 4GiB 3,3V 8-bit"),	0xD7, 0, 4096, 0, LP_OPTIONS},
-	{__NANDSTR("NAND 4GiB 1,8V 16-bit"),	0xB7, 0, 4096, 0, LP_OPTIONS16},
-	{__NANDSTR("NAND 4GiB 3,3V 16-bit"),	0xC7, 0, 4096, 0, LP_OPTIONS16},
+	EXTENDED_ID_NAND(__STR("NAND 4GiB 1,8V 8-bit"),  0xA7, 4096, LP_OPTIONS),
+	EXTENDED_ID_NAND(__STR("NAND 4GiB 3,3V 8-bit"),  0xD7, 4096, LP_OPTIONS),
+	EXTENDED_ID_NAND(__STR("NAND 4GiB 1,8V 16-bit"), 0xB7, 4096, LP_OPTIONS16),
+	EXTENDED_ID_NAND(__STR("NAND 4GiB 3,3V 16-bit"), 0xC7, 4096, LP_OPTIONS16),
 
 	/* 64 Gigabit */
-	{__NANDSTR("NAND 8GiB 1,8V 8-bit"),	0xAE, 0, 8192, 0, LP_OPTIONS},
-	{__NANDSTR("NAND 8GiB 3,3V 8-bit"),	0xDE, 0, 8192, 0, LP_OPTIONS},
-	{__NANDSTR("NAND 8GiB 1,8V 16-bit"),	0xBE, 0, 8192, 0, LP_OPTIONS16},
-	{__NANDSTR("NAND 8GiB 3,3V 16-bit"),	0xCE, 0, 8192, 0, LP_OPTIONS16},
+	EXTENDED_ID_NAND(__STR("NAND 8GiB 1,8V 8-bit"),  0xAE, 8192, LP_OPTIONS),
+	EXTENDED_ID_NAND(__STR("NAND 8GiB 3,3V 8-bit"),  0xDE, 8192, LP_OPTIONS),
+	EXTENDED_ID_NAND(__STR("NAND 8GiB 1,8V 16-bit"), 0xBE, 8192, LP_OPTIONS16),
+	EXTENDED_ID_NAND(__STR("NAND 8GiB 3,3V 16-bit"), 0xCE, 8192, LP_OPTIONS16),
 
 	/* 128 Gigabit */
-	{__NANDSTR("NAND 16GiB 1,8V 8-bit"),	0x1A, 0, 16384, 0, LP_OPTIONS},
-	{__NANDSTR("NAND 16GiB 3,3V 8-bit"),	0x3A, 0, 16384, 0, LP_OPTIONS},
-	{__NANDSTR("NAND 16GiB 1,8V 16-bit"),	0x2A, 0, 16384, 0, LP_OPTIONS16},
-	{__NANDSTR("NAND 16GiB 3,3V 16-bit"),	0x4A, 0, 16384, 0, LP_OPTIONS16},
+	EXTENDED_ID_NAND(__STR("NAND 16GiB 1,8V 8-bit"),  0x1A, 16384, LP_OPTIONS),
+	EXTENDED_ID_NAND(__STR("NAND 16GiB 3,3V 8-bit"),  0x3A, 16384, LP_OPTIONS),
+	EXTENDED_ID_NAND(__STR("NAND 16GiB 1,8V 16-bit"), 0x2A, 16384, LP_OPTIONS16),
+	EXTENDED_ID_NAND(__STR("NAND 16GiB 3,3V 16-bit"), 0x4A, 16384, LP_OPTIONS16),
 
 	/* 256 Gigabit */
-	{__NANDSTR("NAND 32GiB 1,8V 8-bit"),	0x1C, 0, 32768, 0, LP_OPTIONS},
-	{__NANDSTR("NAND 32GiB 3,3V 8-bit"),	0x3C, 0, 32768, 0, LP_OPTIONS},
-	{__NANDSTR("NAND 32GiB 1,8V 16-bit"),	0x2C, 0, 32768, 0, LP_OPTIONS16},
-	{__NANDSTR("NAND 32GiB 3,3V 16-bit"),	0x4C, 0, 32768, 0, LP_OPTIONS16},
+	EXTENDED_ID_NAND(__STR("NAND 32GiB 1,8V 8-bit"),  0x1C, 32768, LP_OPTIONS),
+	EXTENDED_ID_NAND(__STR("NAND 32GiB 3,3V 8-bit"),  0x3C, 32768, LP_OPTIONS),
+	EXTENDED_ID_NAND(__STR("NAND 32GiB 1,8V 16-bit"), 0x2C, 32768, LP_OPTIONS16),
+	EXTENDED_ID_NAND(__STR("NAND 32GiB 3,3V 16-bit"), 0x4C, 32768, LP_OPTIONS16),
 
 	/* 512 Gigabit */
-	{__NANDSTR("NAND 64GiB 1,8V 8-bit"),	0x1E, 0, 65536, 0, LP_OPTIONS},
-	{__NANDSTR("NAND 64GiB 3,3V 8-bit"),	0x3E, 0, 65536, 0, LP_OPTIONS},
-	{__NANDSTR("NAND 64GiB 1,8V 16-bit"),	0x2E, 0, 65536, 0, LP_OPTIONS16},
-	{__NANDSTR("NAND 64GiB 3,3V 16-bit"),	0x4E, 0, 65536, 0, LP_OPTIONS16},
+	EXTENDED_ID_NAND(__STR("NAND 64GiB 1,8V 8-bit"),  0x1E, 65536, LP_OPTIONS),
+	EXTENDED_ID_NAND(__STR("NAND 64GiB 3,3V 8-bit"),  0x3E, 65536, LP_OPTIONS),
+	EXTENDED_ID_NAND(__STR("NAND 64GiB 1,8V 16-bit"), 0x2E, 65536, LP_OPTIONS16),
+	EXTENDED_ID_NAND(__STR("NAND 64GiB 3,3V 16-bit"), 0x4E, 65536, LP_OPTIONS16),
 
-	/*
-	 * Renesas AND 1 Gigabit. Those chips do not support extended id and
-	 * have a strange page/block layout !  The chosen minimum erasesize is
-	 * 4 * 2 * 2048 = 16384 Byte, as those chips have an array of 4 page
-	 * planes 1 block = 2 pages, but due to plane arrangement the blocks
-	 * 0-3 consists of page 0 + 4,1 + 5, 2 + 6, 3 + 7 Anyway JFFS2 would
-	 * increase the eraseblock size so we chose a combined one which can be
-	 * erased in one go There are more speed improvements for reads and
-	 * writes possible, but not implemented now
-	 */
-	{__NANDSTR("AND 128MiB 3,3V 8-bit"),	0x01, 2048, 128, 0x4000,
-	 NAND_IS_AND | NAND_NO_AUTOINCR |NAND_NO_READRDY | NAND_4PAGE_ARRAY |
-	 BBT_AUTO_REFRESH
-	},
-
-	{NULL,}
+	{NULL}
 };
 
-/*
-*	Manufacturer ID list
-*/
+/* Manufacturer IDs */
 struct nand_manufacturers nand_manuf_ids[] = {
-	{NAND_MFR_TOSHIBA, __NANDSTR("Toshiba")},
-	{NAND_MFR_SAMSUNG, __NANDSTR("Samsung")},
-	{NAND_MFR_FUJITSU, __NANDSTR("Fujitsu")},
-	{NAND_MFR_NATIONAL, __NANDSTR("National")},
-	{NAND_MFR_RENESAS, __NANDSTR("Renesas")},
-	{NAND_MFR_STMICRO, __NANDSTR("ST Micro")},
-	{NAND_MFR_HYNIX, __NANDSTR("Hynix")},
-	{NAND_MFR_MICRON, __NANDSTR("Micron")},
-	{NAND_MFR_AMD, __NANDSTR("AMD/Spansion")},
-	{NAND_MFR_MACRONIX, __NANDSTR("Macronix")},
-	{NAND_MFR_EON, __NANDSTR("Eon")},
+	{NAND_MFR_TOSHIBA, "Toshiba"},
+	{NAND_MFR_SAMSUNG, "Samsung"},
+	{NAND_MFR_FUJITSU, "Fujitsu"},
+	{NAND_MFR_NATIONAL, "National"},
+	{NAND_MFR_RENESAS, "Renesas"},
+	{NAND_MFR_STMICRO, "ST Micro"},
+	{NAND_MFR_HYNIX, "Hynix"},
+	{NAND_MFR_MICRON, "Micron"},
+	{NAND_MFR_AMD, "AMD/Spansion"},
+	{NAND_MFR_MACRONIX, "Macronix"},
+	{NAND_MFR_EON, "Eon"},
 	{0x0, "Unknown"}
 };