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authorAndrey Smirnov <andrew.smirnov@gmail.com>2016-02-06 20:04:22 -0800
committerSascha Hauer <s.hauer@pengutronix.de>2016-02-08 08:07:08 +0100
commitb09ee0358cd41b833da9788acf26efdfb6abe40d (patch)
treed08d964622630ca55b02f88751b40ee85deddb27 /drivers/mtd/spi-nor/spi-nor.c
parenta6f73ec52f5c794938aa14b1264375228890f12c (diff)
downloadbarebox-b09ee0358cd41b833da9788acf26efdfb6abe40d.tar.gz
barebox-b09ee0358cd41b833da9788acf26efdfb6abe40d.tar.xz
spi-nor: Port erase timeout fix from Linux
Large SPI-NOR (>2MB) chips reuire more than 40 seconds to perform all-chip erase. This patch adapts 09b6a377687b885565339e60bc62566433a0406f from Linux kernel, which implements simple heuristics in order to calculate appropriate wait time (see orignal commit's description for more details of the fix) Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/mtd/spi-nor/spi-nor.c')
-rw-r--r--drivers/mtd/spi-nor/spi-nor.c37
1 files changed, 34 insertions, 3 deletions
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 27f4abc03e..908aacb6a2 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -15,6 +15,7 @@
#include <driver.h>
#include <errno.h>
#include <linux/err.h>
+#include <linux/sizes.h>
#include <linux/math64.h>
#include <linux/mod_devicetable.h>
#include <linux/mtd/mtd.h>
@@ -25,6 +26,18 @@
#define SPI_NOR_MAX_ID_LEN 6
+/*
+ * For everything but full-chip erase; probably could be much smaller, but kept
+ * around for safety for now
+ */
+#define DEFAULT_READY_WAIT (40 * SECOND)
+
+/*
+ * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
+ * for larger flash
+ */
+#define CHIP_ERASE_2MB_READY_WAIT (40 * SECOND)
+
struct flash_info {
/*
* This array stores the ID bytes.
@@ -228,14 +241,15 @@ static int spi_nor_ready(struct spi_nor *nor)
* Service routine to read status register until ready, or timeout occurs.
* Returns non-zero if error.
*/
-static int spi_nor_wait_till_ready(struct spi_nor *nor)
+static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
+ uint64_t timeout_ns)
{
uint64_t start = get_time_ns();
int timeout = 0;
int ret;
while (!timeout) {
- if (is_timeout(start, 40 * SECOND))
+ if (is_timeout(start, timeout_ns))
timeout = 1;
ret = spi_nor_ready(nor);
@@ -250,6 +264,12 @@ static int spi_nor_wait_till_ready(struct spi_nor *nor)
return -ETIMEDOUT;
}
+static int spi_nor_wait_till_ready(struct spi_nor *nor)
+{
+ return spi_nor_wait_till_ready_with_timeout(nor,
+ DEFAULT_READY_WAIT);
+}
+
/*
* Erase the whole flash memory
*
@@ -318,6 +338,8 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
/* whole-chip erase? */
if (len == mtd->size) {
+ uint64_t timeout;
+
write_enable(nor);
if (erase_chip(nor)) {
@@ -325,7 +347,16 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
goto erase_err;
}
- ret = spi_nor_wait_till_ready(nor);
+ /*
+ * Scale the timeout linearly with the size of the flash, with
+ * a minimum calibrated to an old 2MB flash. We could try to
+ * pull these from CFI/SFDP, but these values should be good
+ * enough for now.
+ */
+ timeout = max(CHIP_ERASE_2MB_READY_WAIT,
+ CHIP_ERASE_2MB_READY_WAIT *
+ (uint64_t)(mtd->size / SZ_2M));
+ ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
if (ret)
goto erase_err;