diff options
| author | Daniel Schultz <d.schultz@phytec.de> | 2016-10-20 15:40:06 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2016-11-11 09:54:13 +0100 |
| commit | 6f58e5cac9742a48ef9e1022eaf6e6b1dbae9b96 (patch) | |
| tree | fc4907c5c2fb80d99fa616c47e0fff4bc797410d /drivers/mtd | |
| parent | 047ee22b894c15a01ed40f358d5c933b6807d880 (diff) | |
| download | barebox-6f58e5cac9742a48ef9e1022eaf6e6b1dbae9b96.tar.gz barebox-6f58e5cac9742a48ef9e1022eaf6e6b1dbae9b96.tar.xz | |
nand: imx6: Changed default NAND clock
The Barebox recognized false bad erase blocks while booting from a
Spansion NAND (1). This error occurred due a to high clock. The
Kernel sets the default NAND clock to 22Mhz. So, to fix this error and
to be more identical with the Kernel, the Barebox should be too.
1: nand: NAND device: Manufacturer ID: 0x01, Chip ID: 0xd3 (AMD/Spansion
S34ML08G2), 1024MiB, page size: 2048, OOB size: 128
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Tested-by: Stefan Lengfeld <s.lengfeld@phytec.de>
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/mtd')
| -rw-r--r-- | drivers/mtd/nand/nand_mxs.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mtd/nand/nand_mxs.c b/drivers/mtd/nand/nand_mxs.c index 01aa06333a..fe955e8af4 100644 --- a/drivers/mtd/nand/nand_mxs.c +++ b/drivers/mtd/nand/nand_mxs.c @@ -2145,7 +2145,7 @@ static int mxs_nand_probe(struct device_d *dev) if (mxs_nand_is_imx6(nand_info)) { clk_disable(nand_info->clk); - clk_set_rate(nand_info->clk, 96000000); + clk_set_rate(nand_info->clk, 22000000); clk_enable(nand_info->clk); nand_info->dma_channel_base = 0; } else { |