net: designware: socfpga: fix phy setup for Arria10

Barebox-version of the Linux v5.2 patch:

    40ae25505fe834648ce4aa70b073ee934942bfdb
    net: stmmac: socfpga: fix phy and ptp_ref setup for Arria10/Stratix10

    On the Arria10, Agilex, and Stratix10 SoC, there are a few differences from
    the Cyclone5 and Arria5:
     - The emac PHY setup bits are in separate registers.
     - The PTP reference clock select mask is different.
     - The register to enable the emac signal from FPGA is different.

    Thus, this patch creates a separate function for setting the phy modes on
    Arria10/Agilex/Stratix10. The separation is based a new DTS binding:
    "altr,socfpga-stmmac-a10-s10".

    Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
    Signed-off-by: David S. Miller <davem@davemloft.net>

The new DTS binding is already part of v2019.10.0 and the driver doesn't
probe on Arria10 without the new binding introduced in this patch.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

1 files changed, 1 insertions, 0 deletions

diff --git a/drivers/net/designware.h b/drivers/net/designware.h
index 305f674bf0..0a6a6bf1a4 100644
--- a/drivers/net/designware.h
+++ b/drivers/net/designware.h
@@ -35,6 +35,7 @@ struct dw_eth_dev {
 
 struct dw_eth_drvdata {
 	bool enh_desc;
+	void *priv;
 };
 
 struct dw_eth_dev *dwc_drv_probe(struct device_d *dev);