[mpc5200 fec] revert to some old version (somehow my play version got into the

              repository). Runtime tested on pcm030

2 files changed, 408 insertions, 554 deletions

diff --git a/drivers/net/fec_mpc5200.c b/drivers/net/fec_mpc5200.c
index 39c3f132db..68142c4e66 100644
--- a/drivers/net/fec_mpc5200.c
+++ b/drivers/net/fec_mpc5200.c
@@ -4,53 +4,21 @@
  *
  * This file is based on mpc4200fec.c,
  * (C) Copyright Motorola, Inc., 2000
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
  */
 
-#define DEBUG
-
 #include <common.h>
-//#include <asm/arch/mpc5xxx.h>
+#include <asm/arch/mpc5xxx.h>
 #include <malloc.h>
 #include <net.h>
 #include <init.h>
 #include <miiphy.h>
 #include <driver.h>
-//#include <asm/arch/sdma.h>
-//#include <asm/arch/fec.h>
-#include <asm-ppc/arch-mpc5200/fec.h>
-//#include <asm/arch/clocks.h>
+#include <asm/arch/sdma.h>
+#include <asm/arch/fec.h>
+#include <asm/arch/clocks.h>
 #include <miiphy.h>
 #include "fec_mpc5200.h"
 
-#include <asm/io.h>
-
-#ifdef CONFIG_ARCH_IMX27
-#include <asm/arch/imx-regs.h>
-#include <clock.h>
-#include <asm/arch/clock.h>
-#include <xfuncs.h>
-#endif
-
-extern int memory_display(char *addr, ulong offs, ulong nbytes, int size);
-
 #define CONFIG_PHY_ADDR 1 /* FIXME */
 
 typedef struct {
@@ -71,38 +39,36 @@ static int fec5xxx_miiphy_read(struct miiphy_device *mdev, uint8_t phyAddr,
 
 	uint32 reg;		/* convenient holder for the PHY register */
 	uint32 phy;		/* convenient holder for the PHY */
-	uint64_t start;
+	int timeout = 0xffff;
 
 	/*
 	 * reading from any PHY's register is done by properly
 	 * programming the FEC's MII data register.
 	 */
-	writel(FEC_IEVENT_MII, &fec->eth->ievent);
 	reg = regAddr << FEC_MII_DATA_RA_SHIFT;
 	phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
 
-	writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg, &fec->eth->mii_data);
+	fec->eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg);
 
 	/*
 	 * wait for the related interrupt
 	 */
-	start = get_time_ns();
-	while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) {
-		if (is_timeout(start, MSECOND)) {
-			printf("Read MDIO failed...\n");
-			return -1;
-		}
+	while ((timeout--) && (!(fec->eth->ievent & FEC_IEVENT_MII))) ;
+
+	if (timeout == 0) {
+		debug("Read MDIO failed...\n");
+		return -1;
 	}
 
 	/*
 	 * clear mii interrupt bit
 	 */
-	writel(FEC_IEVENT_MII, &fec->eth->ievent);
+	fec->eth->ievent = FEC_IEVENT_MII;
 
 	/*
 	 * it's now safe to read the PHY's register
 	 */
-	*retVal = readl(&fec->eth->mii_data);
+	*retVal = (uint16) fec->eth->mii_data;
 
 	return 0;
 }
@@ -115,171 +81,148 @@ static int fec5xxx_miiphy_write(struct miiphy_device *mdev, uint8_t phyAddr,
 
 	uint32 reg;		/* convenient holder for the PHY register */
 	uint32 phy;		/* convenient holder for the PHY */
-	uint64_t start;
+	int timeout = 0xffff;
 
 	reg = regAddr << FEC_MII_DATA_RA_SHIFT;
 	phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
 
-	writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
-		FEC_MII_DATA_TA | phy | reg | data, &fec->eth->mii_data);
+	fec->eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
+			FEC_MII_DATA_TA | phy | reg | data);
 
 	/*
 	 * wait for the MII interrupt
 	 */
-	start = get_time_ns();
-	while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) {
-		if (is_timeout(start, MSECOND)) {
-			printf("Write MDIO failed...\n");
-			return -1;
-		}
+	while ((timeout--) && (!(fec->eth->ievent & FEC_IEVENT_MII))) ;
+
+	if (timeout == 0) {
+		debug("Write MDIO failed...\n");
+		return -1;
 	}
 
 	/*
 	 * clear MII interrupt bit
 	 */
-	writel(FEC_IEVENT_MII, &fec->eth->ievent);
-
-	return 0;
-}
-
-#ifdef CONFIG_MPC5200
-static int mpc5xxx_fec_rx_task_enable(mpc5xxx_fec_priv *fec)
-{
-	SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
-	return 0;
-}
-
-static int mpc5xxx_fec_rx_task_disable(mpc5xxx_fec_priv *fec)
-{
-	SDMA_TASK_DISABLE(FEC_RECV_TASK_NO);
-	return 0;
-}
-
-static int mpc5xxx_fec_tx_task_enable(mpc5xxx_fec_priv *fec)
-{
-	SDMA_TASK_ENABLE(FEC_XMIT_TASK_NO);
-	return 0;
-}
-
-static int mpc5xxx_fec_tx_task_disable(mpc5xxx_fec_priv *fec)
-{
-	SDMA_TASK_DISABLE(FEC_XMIT_TASK_NO);
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_ARCH_IMX27
-static int mpc5xxx_fec_rx_task_enable(mpc5xxx_fec_priv *fec)
-{
-	writel(1 << 24, &fec->eth->r_des_active);
-	return 0;
-}
-
-static int mpc5xxx_fec_rx_task_disable(mpc5xxx_fec_priv *fec)
-{
-	return 0;
-}
+	fec->eth->ievent = FEC_IEVENT_MII;
 
-static int mpc5xxx_fec_tx_task_enable(mpc5xxx_fec_priv *fec)
-{
-	writel(1 << 24, &fec->eth->x_des_active);
-	return 0;
-}
-
-static int mpc5xxx_fec_tx_task_disable(mpc5xxx_fec_priv *fec)
-{
 	return 0;
 }
-#endif
 
-/**
- * allocate and link buffers for the receive task
- * @param[in] fec all we know about the device yet
- * @param[in] count receive buffer count to be allocated
- * @param[in] size size of each receive buffer
- * @return 0 on success
- *
- * We need some alignment for the buffers. Thy must be
- * aligned to a specific boundary each. See RDB_ALIGNMENT
- */
-static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec, int count, int size)
+static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec)
 {
 	int ix;
+	char *data;
 	static int once = 0;
-	uint32 p;
-
-	printf("%s\n", __FUNCTION__);
-
-	size += RDB_ALIGNMENT;	/* enlarge the size for alignment */
 
-	for (ix = 0; ix < count; ix++) {
+	for (ix = 0; ix < FEC_RBD_NUM; ix++) {
 		if (!once) {
-			p = (uint32)xzalloc(size);
-			p += RDB_ALIGNMENT - 1;
-			p &= ~(RDB_ALIGNMENT - 1);
-			writel(p, &fec->rbdBase[ix].dataPointer);
+			data = (char *)malloc(FEC_MAX_PKT_SIZE);
+			if (data == NULL) {
+				printf ("RBD INIT FAILED\n");
+				return -1;
+			}
+			fec->rbdBase[ix].dataPointer = (uint32)data;
 		}
-		writew(FEC_RBD_EMPTY, &fec->rbdBase[ix].status);
-		writew(0, &fec->rbdBase[ix].dataLength);
+		fec->rbdBase[ix].status = FEC_RBD_EMPTY;
+		fec->rbdBase[ix].dataLength = 0;
 	}
 	once ++;
 
 	/*
 	 * have the last RBD to close the ring
 	 */
-	writew(FEC_RBD_WRAP | readl(&fec->rbdBase[ix - 1].status), &fec->rbdBase[ix - 1].status);
+	fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP;
 	fec->rbdIndex = 0;
 
 	return 0;
 }
 
-/**
- * initialize buffers for the transmit task
- * @param[in] fec all we know about the device yet
- *
- * Nothing special here to do. We ony using one bufffer
- * for all transmit operations.
- */
 static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec)
 {
-	writew(FEC_TBD_WRAP, &fec->tbdBase[0].status);
+	int ix;
+
+	for (ix = 0; ix < FEC_TBD_NUM; ix++) {
+		fec->tbdBase[ix].status = 0;
+	}
+
+	/*
+	 * Have the last TBD to close the ring
+	 */
+	fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP;
+
+	/*
+	 * Initialize some indices
+	 */
+	fec->tbdIndex = 0;
+	fec->usedTbdIndex = 0;
+	fec->cleanTbdNum = FEC_TBD_NUM;
 }
 
-/**
- * Mark the given read buffer descriptor as free
- * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
- * @param[in] pRbd buffer descriptor to mark free again
- */
-static void mpc5xxx_fec_rbd_clean(int last, FEC_RBD *pRbd)
+static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv *fec, volatile FEC_RBD * pRbd)
 {
 	/*
 	 * Reset buffer descriptor as empty
 	 */
-	if (last)
-		writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &pRbd->status);
+	if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
+		pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
 	else
-		writew(FEC_RBD_EMPTY, &pRbd->status);
+		pRbd->status = FEC_RBD_EMPTY;
+
+	pRbd->dataLength = 0;
+
+	/*
+	 * Now, we have an empty RxBD, restart the SmartDMA receive task
+	 */
+	SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
+
+	/*
+	 * Increment BD count
+	 */
+	fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
+}
+
+static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv *fec)
+{
+	volatile FEC_TBD *pUsedTbd;
+
 	/*
-	 * no data in it
+	 * process all the consumed TBDs
 	 */
-	writew(0, &pRbd->dataLength);
+	while (fec->cleanTbdNum < FEC_TBD_NUM) {
+		pUsedTbd = &fec->tbdBase[fec->usedTbdIndex];
+		if (pUsedTbd->status & FEC_TBD_READY) {
+			debug("Cannot clean TBD %d, in use\n", fec->cleanTbdNum);
+			return;
+		}
+
+		/*
+		 * clean this buffer descriptor
+		 */
+		if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
+			pUsedTbd->status = FEC_TBD_WRAP;
+		else
+			pUsedTbd->status = 0;
+
+		/*
+		 * update some indeces for a correct handling of the TBD ring
+		 */
+		fec->cleanTbdNum++;
+		fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
+	}
 }
 
-static int mpc5xxx_fec_get_hwaddr(struct eth_device *dev, unsigned char *mac)
+static int mpc5xxx_fec_get_ethaddr(struct eth_device *dev, unsigned char *mac)
 {
 	/* no eeprom */
 	return -1;
 }
 
-static int mpc5xxx_fec_set_hwaddr(struct eth_device *dev, unsigned char *mac)
+static int mpc5xxx_fec_set_ethaddr(struct eth_device *dev, unsigned char *mac)
 {
 	mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
-//#define WTF_IS_THIS
-#ifdef WTF_IS_THIS
-	uint32 crc = 0xffffffff;	/* initial value */
 	uint8 currByte;			/* byte for which to compute the CRC */
 	int byte;			/* loop - counter */
 	int bit;			/* loop - counter */
+	uint32 crc = 0xffffffff;	/* initial value */
 
 	/*
 	 * The algorithm used is the following:
@@ -321,17 +264,12 @@ static int mpc5xxx_fec_set_hwaddr(struct eth_device *dev, unsigned char *mac)
 		fec->eth->iaddr1 = 0;
 		fec->eth->iaddr2 = (1 << crc);
 	}
-#else
-	writel(0, &fec->eth->iaddr1);
-	writel(0, &fec->eth->iaddr2);
-	writel(0, &fec->eth->gaddr1);
-	writel(0, &fec->eth->gaddr2);
-#endif
+
 	/*
 	 * Set physical address
 	 */
-	writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], &fec->eth->paddr1);
-	writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
+	fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
+	fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
 
         return 0;
 }
@@ -339,26 +277,25 @@ static int mpc5xxx_fec_set_hwaddr(struct eth_device *dev, unsigned char *mac)
 static int mpc5xxx_fec_init(struct eth_device *dev)
 {
 	mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
-#ifdef CONFIG_MPC5200
 	struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
-#endif
+
 	debug("mpc5xxx_fec_init... Begin\n");
 
 	/*
 	 * Initialize RxBD/TxBD rings
 	 */
-	mpc5xxx_fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
+	mpc5xxx_fec_rbd_init(fec);
 	mpc5xxx_fec_tbd_init(fec);
 
 	/*
 	 * Clear FEC-Lite interrupt event register(IEVENT)
 	 */
-	writel(0xffffffff, &fec->eth->ievent);
+	fec->eth->ievent = 0xffffffff;
 
 	/*
 	 * Set interrupt mask register
 	 */
-	writel(0x00000000, &fec->eth->imask);
+	fec->eth->imask = 0x00000000;
 
 	/*
 	 * Set FEC-Lite receive control register(R_CNTRL):
@@ -367,94 +304,84 @@ static int mpc5xxx_fec_init(struct eth_device *dev)
 		/*
 		 * Frame length=1518; 7-wire mode
 		 */
-		writel(0x05ee0020, &fec->eth->r_cntrl);	/* FIXME 0x05ee0000 */
+		fec->eth->r_cntrl = 0x05ee0020;	/*0x05ee0000;FIXME */
 	} else {
 		/*
 		 * Frame length=1518; MII mode;
 		 */
-		writel(0x05ee0024, &fec->eth->r_cntrl);	/* FIXME 0x05ee0004 */
+		fec->eth->r_cntrl = 0x05ee0024;	/*0x05ee0004;FIXME */
+	}
 
+	if (fec->xcv_type != SEVENWIRE) {
 		/*
 		 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
 		 * and do not drop the Preamble.
 		 */
-#ifdef CONFIG_MPC5200
-		writel(((get_ipb_clock() >> 20) / 5) << 1, &fec->eth->mii_speed);	/* No MII for 7-wire mode */
-#endif
-#ifdef CONFIG_ARCH_IMX27
-		writel(((imx_get_ahbclk() >> 20) / 5) << 1, &fec->eth->mii_speed);	/* No MII for 7-wire mode */
-#endif
+		fec->eth->mii_speed = (((get_ipb_clock() >> 20) / 5) << 1);	/* No MII for 7-wire mode */
 	}
 
 	/*
 	 * Set Opcode/Pause Duration Register
 	 */
-	writel(0x00010020, &fec->eth->op_pause);	/* FIXME 0xffff0020; */
+	fec->eth->op_pause = 0x00010020;	/*FIXME 0xffff0020; */
 
-#ifdef CONFIG_MPC5200
 	/*
 	 * Set Rx FIFO alarm and granularity value
 	 */
-	writel(0x0c000000 | (readl(&fec->eth->rfifo_cntrl) & ~0x0f000000)), &fec->eth->rfifo_cntrl);
-	writel(0x0000030c, &fec->eth->rfifo_alarm);
+	fec->eth->rfifo_cntrl = 0x0c000000
+				| (fec->eth->rfifo_cntrl & ~0x0f000000);
+	fec->eth->rfifo_alarm = 0x0000030c;
 
-	if (readl(&fec->eth->rfifo_status) & 0x00700000 ) {
+	if (fec->eth->rfifo_status & 0x00700000 ) {
 		debug("mpc5xxx_fec_init() RFIFO error\n");
 	}
 
 	/*
 	 * Set Tx FIFO granularity value
 	 */
-	writel(0x0c000000 | (readl(&fec->eth->tfifo_cntrl)& ~0x0f000000), &fec->eth->tfifo_cntrl);
+	fec->eth->tfifo_cntrl = 0x0c000000
+				| (fec->eth->tfifo_cntrl & ~0x0f000000);
 
-	debug("tfifo_status: 0x%08x\n", readl(&fec->eth->tfifo_status));
-	debug("tfifo_alarm: 0x%08x\n", readl(&fec->eth->tfifo_alarm));
+	debug("tfifo_status: 0x%08x\n", fec->eth->tfifo_status);
+	debug("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm);
 
 	/*
 	 * Set transmit fifo watermark register(X_WMRK), default = 64
 	 */
-	writel(0x00000080, &fec->eth->tfifo_alarm);
+	fec->eth->tfifo_alarm = 0x00000080;
+	fec->eth->x_wmrk = 0x2;
 
 	/*
-	 * Turn ON cheater FSM: ????
+	 * Set multicast address filter
 	 */
-	writel(0x03000000, &fec->eth->xmit_fsm);
-#endif
-
-	writel(0x2, &fec->eth->x_wmrk);
+	fec->eth->gaddr1 = 0x00000000;
+	fec->eth->gaddr2 = 0x00000000;
 
 	/*
-	 * Set multicast address filter
+	 * Turn ON cheater FSM: ????
 	 */
-	writel(0x00000000, &fec->eth->gaddr1);
-	writel(0x00000000, &fec->eth->gaddr2);
+	fec->eth->xmit_fsm = 0x03000000;
 
-#ifdef CONFIG_MPC5200
 	/*
 	 * Set priority of different initiators
 	 */
 	sdma->IPR0 = 7;		/* always */
 	sdma->IPR3 = 6;		/* Eth RX */
 	sdma->IPR4 = 5;		/* Eth Tx */
-#endif
 
-#ifdef CONFIG_ARCH_IMX27
-	writel(2048-16, &fec->eth->emrbr);
-#endif
 	/*
 	 * Clear SmartDMA task interrupt pending bits
 	 */
-//	SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO);
+	SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO);
 
 	/*
 	 * Initialize SmartDMA parameters stored in SRAM
 	 */
-#ifdef CONFIG_MPC5200
 	*(volatile int *)FEC_TBD_BASE = (int)fec->tbdBase;
 	*(volatile int *)FEC_RBD_BASE = (int)fec->rbdBase;
 	*(volatile int *)FEC_TBD_NEXT = (int)fec->tbdBase;
 	*(volatile int *)FEC_RBD_NEXT = (int)fec->rbdBase;
-#endif
+
 	debug("mpc5xxx_fec_init... Done \n");
 
 	if (fec->xcv_type != SEVENWIRE)
@@ -467,8 +394,6 @@ static int mpc5xxx_fec_open(struct eth_device *edev)
 {
 	mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)edev->priv;
 
-	printf("%s\n", __FUNCTION__);
-
 #if defined(CONFIG_MPC5200)
 	struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
 	/*
@@ -478,27 +403,17 @@ static int mpc5xxx_fec_open(struct eth_device *edev)
 	 sdma->PtdCntrl |= 0x00000001;
 #endif
 
-#if 0
-	writel(0x00000000, &fec->eth->x_cntrl);	/* half-duplex, heartbeat disabled */
-#else
-	writel(1 << 2, &fec->eth->x_cntrl);	/* full-duplex, heartbeat disabled */
-#endif
-
-	fec->rbdIndex = 0;
+	fec->eth->x_cntrl = 0x00000000;	/* half-duplex, heartbeat disabled */
 
 	/*
 	 * Enable FEC-Lite controller
 	 */
-#if defined(CONFIG_MPC5200)
-	writel(0x00000006 | readl(&fec->eth->ecntrl), &fec->eth->ecntrl);
-#endif
-#if defined(CONFIG_ARCH_IMX27)
-	writel(0x00000002 | readl(&fec->eth->ecntrl), &fec->eth->ecntrl);
-#endif
+	fec->eth->ecntrl |= 0x00000006;
+
 	/*
 	 * Enable SmartDMA receive task
 	 */
-	mpc5xxx_fec_rx_task_enable(fec);
+	SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
 
 	if (fec->xcv_type != SEVENWIRE) {
 		miiphy_wait_aneg(&fec->miiphy);
@@ -519,21 +434,20 @@ static void mpc5xxx_fec_halt(struct eth_device *dev)
 	/*
 	 * issue graceful stop command to the FEC transmitter if necessary
 	 */
-	writel(0x00000001 | readl(&fec->eth->x_cntrl), &fec->eth->x_cntrl);
+	fec->eth->x_cntrl |= 0x00000001;
 
 	/*
 	 * wait for graceful stop to register
 	 */
-	while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
-		;
+	while ((counter--) && (!(fec->eth->ievent & FEC_IEVENT_GRA))) ;
 
 	/*
 	 * Disable SmartDMA tasks
 	 */
-	mpc5xxx_fec_tx_task_disable(fec);
-	mpc5xxx_fec_rx_task_disable(fec);
+	SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
+	SDMA_TASK_DISABLE (FEC_RECV_TASK_NO);
 
-#ifdef CONFIG_MPC5200
+#if defined(CONFIG_MPC5200)
 	/*
 	 * Turn on COMM bus prefetch in the MGT5200 BestComm after we're
 	 * done. It doesn't work w/ the current receive task.
@@ -544,17 +458,15 @@ static void mpc5xxx_fec_halt(struct eth_device *dev)
 	/*
 	 * Disable the Ethernet Controller
 	 */
-	writel(0, &fec->eth->ecntrl);
+	fec->eth->ecntrl &= 0xfffffffd;
 
-#ifdef CONFIG_MPC5200
 	/*
 	 * Clear FIFO status registers
 	 */
-	writel(0x00700000 & readl(&fec->eth->rfifo_status), &fec->eth->rfifo_status);
-	writel(0x00700000 & readl(&fec->eth->tfifo_status), &fec->eth->tfifo_status);
-#endif
+	fec->eth->rfifo_status &= 0x00700000;
+	fec->eth->tfifo_status &= 0x00700000;
 
-//	writel(0x01000000, &fec->eth->reset_cntrl);
+//	fec->eth->reset_cntrl = 0x01000000;
 
 	debug("Ethernet task stopped\n");
 }
@@ -562,39 +474,39 @@ static void mpc5xxx_fec_halt(struct eth_device *dev)
 #ifdef DEBUG_FIFO
 static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec)
 {
-	if ((readl(&fec->eth->tfifo_lrf_ptr) != readl(&fec->eth->tfifo_lwf_ptr))
-		|| (readl(&fec->eth->tfifo_rdptr) != readl(&fec->eth->tfifo_wrptr))) {
-
-		printf("ecntrl:   0x%08x\n", readl(&fec->eth->ecntrl));
-		printf("ievent:   0x%08x\n", readl(&fec->eth->ievent));
-		printf("x_status: 0x%08x\n", readl(&fec->eth->x_status));
-		printf("tfifo: status  0x%08x\n", readl(&fec->eth->tfifo_status));
-
-		printf("       control 0x%08x\n", readl(&fec->eth->tfifo_cntrl));
-		printf("       lrfp    0x%08x\n", readl(&fec->eth->tfifo_lrf_ptr));
-		printf("       lwfp    0x%08x\n", readl(&fec->eth->tfifo_lwf_ptr));
-		printf("       alarm   0x%08x\n", readl(&fec->eth->tfifo_alarm));
-		printf("       readptr 0x%08x\n", readl(&fec->eth->tfifo_rdptr));
-		printf("       writptr 0x%08x\n", readl(&fec->eth->tfifo_wrptr));
+	if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
+		|| (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
+
+		printf("ecntrl:   0x%08x\n", fec->eth->ecntrl);
+		printf("ievent:   0x%08x\n", fec->eth->ievent);
+		printf("x_status: 0x%08x\n", fec->eth->x_status);
+		printf("tfifo: status  0x%08x\n", fec->eth->tfifo_status);
+
+		printf("       control 0x%08x\n", fec->eth->tfifo_cntrl);
+		printf("       lrfp    0x%08x\n", fec->eth->tfifo_lrf_ptr);
+		printf("       lwfp    0x%08x\n", fec->eth->tfifo_lwf_ptr);
+		printf("       alarm   0x%08x\n", fec->eth->tfifo_alarm);
+		printf("       readptr 0x%08x\n", fec->eth->tfifo_rdptr);
+		printf("       writptr 0x%08x\n", fec->eth->tfifo_wrptr);
 	}
 }
 
 static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec)
 {
-	if ((readl(&fec->eth->rfifo_lrf_ptr) != readl(&fec->eth->rfifo_lwf_ptr))
-		|| (readl(&fec->eth->rfifo_rdptr) != readl(&fec->eth->rfifo_wrptr))) {
-
-		printf("ecntrl:   0x%08x\n", readl(&fec->eth->ecntrl));
-		printf("ievent:   0x%08x\n", readl(&fec->eth->ievent));
-		printf("x_status: 0x%08x\n", readl(&fec->eth->x_status));
-		printf("rfifo: status  0x%08x\n", readl(&fec->eth->rfifo_status));
-
-		printf("       control 0x%08x\n", readl(&fec->eth->rfifo_cntrl));
-		printf("       lrfp    0x%08x\n", readl(&fec->eth->rfifo_lrf_ptr));
-		printf("       lwfp    0x%08x\n", readl(&fec->eth->rfifo_lwf_ptr));
-		printf("       alarm   0x%08x\n", readl(&fec->eth->rfifo_alarm));
-		printf("       readptr 0x%08x\n", readl(&fec->eth->rfifo_rdptr));
-		printf("       writptr 0x%08x\n", readl(&fec->eth->rfifo_wrptr));
+	if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
+		|| (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
+
+		printf("ecntrl:   0x%08x\n", fec->eth->ecntrl);
+		printf("ievent:   0x%08x\n", fec->eth->ievent);
+		printf("x_status: 0x%08x\n", fec->eth->x_status);
+		printf("rfifo: status  0x%08x\n", fec->eth->rfifo_status);
+
+		printf("       control 0x%08x\n", fec->eth->rfifo_cntrl);
+		printf("       lrfp    0x%08x\n", fec->eth->rfifo_lrf_ptr);
+		printf("       lwfp    0x%08x\n", fec->eth->rfifo_lwf_ptr);
+		printf("       alarm   0x%08x\n", fec->eth->rfifo_alarm);
+		printf("       readptr 0x%08x\n", fec->eth->rfifo_rdptr);
+		printf("       writptr 0x%08x\n", fec->eth->rfifo_wrptr);
 	}
 }
 #else
@@ -602,7 +514,7 @@ static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec)
 {
 }
 
-static void __maybe_unused rfifo_print(char *devname, mpc5xxx_fec_priv *fec)
+static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec)
 {
 }
 #endif /* DEBUG_FIFO */
@@ -617,13 +529,16 @@ static int mpc5xxx_fec_send(struct eth_device *dev, void *eth_data,
 	mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
 	volatile FEC_TBD *pTbd;
 
-//	printf("%s length=%d data=0x%08x\n", __FUNCTION__, data_length, eth_data);
-
 #ifdef DEBUG_FIFO
 	debug_fifo("tbd status: 0x%04x\n", fec->tbdBase[0].status);
 	tfifo_print(dev->name, fec);
 #endif
 	/*
+	 * Clear Tx BD ring at first
+	 */
+	mpc5xxx_fec_tbd_scrub(fec);
+
+	/*
 	 * Check for valid length of data.
 	 */
 	if ((data_length > 1500) || (data_length <= 0)) {
@@ -631,17 +546,41 @@ static int mpc5xxx_fec_send(struct eth_device *dev, void *eth_data,
 	}
 
 	/*
+	 * Check the number of vacant TxBDs.
+	 */
+	if (fec->cleanTbdNum < 1) {
+		printf("No available TxBDs ...\n");
+		return -1;
+	}
+
+	/*
 	 * Get the first TxBD to send the mac header
 	 */
-	pTbd = &fec->tbdBase[0];
+	pTbd = &fec->tbdBase[fec->tbdIndex];
 	pTbd->dataLength = data_length;
 	pTbd->dataPointer = (uint32)eth_data;
-	pTbd->status = FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY | FEC_TBD_WRAP;
+	pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
+	fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
+
+	/*
+	 * Kick the MII i/f
+	 */
+	if (fec->xcv_type != SEVENWIRE) {
+		uint16 phyStatus;
+		fec5xxx_miiphy_read(&fec->miiphy, 0, 0x1, &phyStatus);
+	}
 
 	/*
 	 * Enable SmartDMA transmit task
 	 */
-	mpc5xxx_fec_tx_task_enable(fec);
+
+//	tfifo_print(dev->name, fec);
+
+	SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
+
+//	tfifo_print(dev->name, fec);
+
+	fec->cleanTbdNum -= 1;
 
 	/*
 	 * wait until frame is sent .
@@ -659,35 +598,33 @@ static int mpc5xxx_fec_recv(struct eth_device *dev)
 	 * This command pulls one frame from the card
 	 */
 	mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
-	FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex];
+	volatile FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex];
 	unsigned long ievent;
 	int frame_length, len = 0;
 	NBUF *frame;
 	uchar buff[FEC_MAX_PKT_SIZE];
 
-//	printf("%s\n", __FUNCTION__);
 	/*
 	 * Check if any critical events have happened
 	 */
-	ievent = readl(&fec->eth->ievent);
-	writel(ievent, &fec->eth->ievent);
+	ievent = fec->eth->ievent;
+	fec->eth->ievent = ievent;
 	if (ievent & (FEC_IEVENT_BABT | FEC_IEVENT_XFIFO_ERROR |
 				FEC_IEVENT_RFIFO_ERROR)) {
 		/* BABT, Rx/Tx FIFO errors */
 		mpc5xxx_fec_halt(dev);
 		mpc5xxx_fec_init(dev);
-		printf("some error: 0x%08x\n", ievent);
 		return 0;
 	}
 	if (ievent & FEC_IEVENT_HBERR) {
 		/* Heartbeat error */
-		writel(0x00000001 | readl(&fec->eth->x_cntrl), &fec->eth->x_cntrl);
+		fec->eth->x_cntrl |= 0x00000001;
 	}
 	if (ievent & FEC_IEVENT_GRA) {
 		/* Graceful stop complete */
-		if (readl(&fec->eth->x_cntrl) & 0x00000001) {
+		if (fec->eth->x_cntrl & 0x00000001) {
 			mpc5xxx_fec_halt(dev);
-			writel(~0x00000001 & readl(&fec->eth->x_cntrl), &fec->eth->x_cntrl);
+			fec->eth->x_cntrl &= ~0x00000001;
 			mpc5xxx_fec_init(dev);
 		}
 	}
@@ -695,49 +632,37 @@ static int mpc5xxx_fec_recv(struct eth_device *dev)
 	if (!(pRbd->status & FEC_RBD_EMPTY)) {
 		if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) &&
 			((pRbd->dataLength - 4) > 14)) {
-			printf("read from %d (0x%08x) rbd=0x%08x", fec->rbdIndex, pRbd->dataPointer, pRbd);
 
 			/*
 			 * Get buffer address and size
 			 */
 			frame = (NBUF *)pRbd->dataPointer;
 			frame_length = pRbd->dataLength - 4;
-			printf(" len=%d\n", frame_length);
-#define DEBUG_RX_HEADER
+
 #ifdef DEBUG_RX_HEADER
 			{
-				printf("recv data hdr:\n");
-				memory_display(frame->data, 0, frame_length, 1);
+				int i;
+				printf("recv data hdr:");
+				for (i = 0; i < 14; i++)
+					printf("%02x ", *(frame->head + i));
+				printf("\n");
 			}
 #endif
 			/*
 			 *  Fill the buffer and pass it to upper layers
 			 */
-#ifdef CONFIG_MPC5200
 			memcpy(buff, frame->head, 14);
 			memcpy(buff + 14, frame->data, frame_length);
-#endif
-#ifdef CONFIG_ARCH_IMX27
-			memcpy(buff, frame->data, frame_length);
-#endif
 			NetReceive(buff, frame_length);
 			len = frame_length;
-		} else {
-			if (pRbd->status & FEC_RBD_ERR) {
-				printf("error frame: 0x%08x 0x%08x\n", pRbd, pRbd->status);
-			}
 		}
 		/*
-		 * free the current buffer, restart the engine and move
-		 * forward to the next buffer
+		 * Reset buffer descriptor as empty
 		 */
-		mpc5xxx_fec_rbd_clean(fec->rbdIndex == (FEC_RBD_NUM - 1) ? 1 : 0, pRbd);
-		mpc5xxx_fec_rx_task_enable(fec);
-		fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
-
+		mpc5xxx_fec_rbd_clean(fec, pRbd);
 	}
 
-//	SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO);
+	SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO);
 	return len;
 }
 
@@ -747,11 +672,6 @@ int mpc5xxx_fec_probe(struct device_d *dev)
         struct eth_device *edev;
 	mpc5xxx_fec_priv *fec;
 
-	printf("%s\n", __FUNCTION__);
-
-#ifdef CONFIG_ARCH_IMX27
-	PCCR0 |= PCCR0_FEC_EN;
-#endif
         edev = (struct eth_device *)malloc(sizeof(struct eth_device));
         dev->type_data = edev;
 	fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec));
@@ -762,40 +682,19 @@ int mpc5xxx_fec_probe(struct device_d *dev)
 	edev->send = mpc5xxx_fec_send,
 	edev->recv = mpc5xxx_fec_recv,
 	edev->halt = mpc5xxx_fec_halt,
-	edev->get_ethaddr = mpc5xxx_fec_get_hwaddr,
-	edev->set_ethaddr = mpc5xxx_fec_set_hwaddr,
+	edev->get_ethaddr = mpc5xxx_fec_get_ethaddr,
+	edev->set_ethaddr = mpc5xxx_fec_set_ethaddr,
 
 	fec->eth = (ethernet_regs *)dev->map_base;
-
-#ifdef CONFIG_MPC5200
 	fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
 	fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
-#endif
-#ifdef CONFIG_ARCH_IMX27
-	/* Reset chip. FIXME: shouldn't it be done for mpc5200 aswell? */
-	writel(1, &fec->eth->ecntrl);
-	while(readl(&fec->eth->ecntrl) & 1) {
-		udelay(10);
-	}
-
-	{
-		unsigned long base;
-	
-		base = ((unsigned long)xzalloc(sizeof(FEC_TBD) + 32) + 31) & ~0x1f;
-		fec->tbdBase = (FEC_TBD *)base;
-		writel(fec->tbdBase, &fec->eth->etdsr);
-		base = ((unsigned long)xzalloc(FEC_RBD_NUM * sizeof(FEC_RBD) + 32) + 31) & ~0x1f;
-		fec->rbdBase = (FEC_RBD *)base;
-		writel(fec->rbdBase, &fec->eth->erdsr);
-	}
-#endif
 
 	fec->xcv_type = pdata->xcv_type;
 
 	sprintf(dev->name, "FEC ETHERNET");
-#ifdef CONFIG_MPC5200
+
 	loadtask(0, 2);
-#endif
+
 	if (fec->xcv_type != SEVENWIRE) {
 		fec->miiphy.read = fec5xxx_miiphy_read;
 		fec->miiphy.write = fec5xxx_miiphy_write;
@@ -824,8 +723,3 @@ static int mpc5xxx_fec_register(void)
 
 device_initcall(mpc5xxx_fec_register);
 
-/**
- * @file
- * @brief Network driver for FreeScale's FEC implementation.
- * This type of hardware can be found on MPC52xx and i.MX27 CPUs
- */
diff --git a/drivers/net/fec_mpc5200.h b/drivers/net/fec_mpc5200.h
index 39547dcdb7..62fb1cf463 100644
--- a/drivers/net/fec_mpc5200.h
+++ b/drivers/net/fec_mpc5200.h
@@ -15,194 +15,188 @@ typedef unsigned long uint32;
 typedef unsigned short uint16;
 typedef unsigned char uint8;
 
-/**
- * Layout description of the FEC
- */
 typedef struct ethernet_register_set {
 
 /* [10:2]addr = 00 */
 
 /*  Control and status Registers (offset 000-1FF) */
 
-	uint32 fec_id;			/* MBAR_ETH + 0x000 */
-	uint32 ievent;			/* MBAR_ETH + 0x004 */
-	uint32 imask;			/* MBAR_ETH + 0x008 */
-
-	uint32 RES0[1];			/* MBAR_ETH + 0x00C */
-	uint32 r_des_active;		/* MBAR_ETH + 0x010 */
-	uint32 x_des_active;		/* MBAR_ETH + 0x014 */
-	uint32 r_des_active_cl;		/* MBAR_ETH + 0x018 */
-	uint32 x_des_active_cl;		/* MBAR_ETH + 0x01C */
-	uint32 ivent_set;		/* MBAR_ETH + 0x020 */
-	uint32 ecntrl;			/* MBAR_ETH + 0x024 */
-
-	uint32 RES1[6];			/* MBAR_ETH + 0x028-03C */
-	uint32 mii_data;		/* MBAR_ETH + 0x040 */
-	uint32 mii_speed;		/* MBAR_ETH + 0x044 */
-	uint32 mii_status;		/* MBAR_ETH + 0x048 */
-
-	uint32 RES2[5];			/* MBAR_ETH + 0x04C-05C */
-	uint32 mib_data;		/* MBAR_ETH + 0x060 */
-	uint32 mib_control;		/* MBAR_ETH + 0x064 */
-
-	uint32 RES3[6];			/* MBAR_ETH + 0x068-7C */
-	uint32 r_activate;		/* MBAR_ETH + 0x080 */
-	uint32 r_cntrl;			/* MBAR_ETH + 0x084 */
-	uint32 r_hash;			/* MBAR_ETH + 0x088 */
-	uint32 r_data;			/* MBAR_ETH + 0x08C */
-	uint32 ar_done;			/* MBAR_ETH + 0x090 */
-	uint32 r_test;			/* MBAR_ETH + 0x094 */
-	uint32 r_mib;			/* MBAR_ETH + 0x098 */
-	uint32 r_da_low;		/* MBAR_ETH + 0x09C */
-	uint32 r_da_high;		/* MBAR_ETH + 0x0A0 */
-
-	uint32 RES4[7];			/* MBAR_ETH + 0x0A4-0BC */
-	uint32 x_activate;		/* MBAR_ETH + 0x0C0 */
-	uint32 x_cntrl;			/* MBAR_ETH + 0x0C4 */
-	uint32 backoff;			/* MBAR_ETH + 0x0C8 */
-	uint32 x_data;			/* MBAR_ETH + 0x0CC */
-	uint32 x_status;		/* MBAR_ETH + 0x0D0 */
-	uint32 x_mib;			/* MBAR_ETH + 0x0D4 */
-	uint32 x_test;			/* MBAR_ETH + 0x0D8 */
-	uint32 fdxfc_da1;		/* MBAR_ETH + 0x0DC */
-	uint32 fdxfc_da2;		/* MBAR_ETH + 0x0E0 */
-	uint32 paddr1;			/* MBAR_ETH + 0x0E4 */
-	uint32 paddr2;			/* MBAR_ETH + 0x0E8 */
-	uint32 op_pause;		/* MBAR_ETH + 0x0EC */
-
-	uint32 RES5[4];			/* MBAR_ETH + 0x0F0-0FC */
-	uint32 instr_reg;		/* MBAR_ETH + 0x100 */
-	uint32 context_reg;		/* MBAR_ETH + 0x104 */
-	uint32 test_cntrl;		/* MBAR_ETH + 0x108 */
-	uint32 acc_reg;			/* MBAR_ETH + 0x10C */
-	uint32 ones;			/* MBAR_ETH + 0x110 */
-	uint32 zeros;			/* MBAR_ETH + 0x114 */
-	uint32 iaddr1;			/* MBAR_ETH + 0x118 */
-	uint32 iaddr2;			/* MBAR_ETH + 0x11C */
-	uint32 gaddr1;			/* MBAR_ETH + 0x120 */
-	uint32 gaddr2;			/* MBAR_ETH + 0x124 */
-	uint32 random;			/* MBAR_ETH + 0x128 */
-	uint32 rand1;			/* MBAR_ETH + 0x12C */
-	uint32 tmp;			/* MBAR_ETH + 0x130 */
-
-	uint32 RES6[3];			/* MBAR_ETH + 0x134-13C */
-	uint32 fifo_id;			/* MBAR_ETH + 0x140 */
-	uint32 x_wmrk;			/* MBAR_ETH + 0x144 */
-	uint32 fcntrl;			/* MBAR_ETH + 0x148 */
-	uint32 r_bound;			/* MBAR_ETH + 0x14C */
-	uint32 r_fstart;		/* MBAR_ETH + 0x150 */
-	uint32 r_count;			/* MBAR_ETH + 0x154 */
-	uint32 r_lag;			/* MBAR_ETH + 0x158 */
-	uint32 r_read;			/* MBAR_ETH + 0x15C */
-	uint32 r_write;			/* MBAR_ETH + 0x160 */
-	uint32 x_count;			/* MBAR_ETH + 0x164 */
-	uint32 x_lag;			/* MBAR_ETH + 0x168 */
-	uint32 x_retry;			/* MBAR_ETH + 0x16C */
-	uint32 x_write;			/* MBAR_ETH + 0x170 */
-	uint32 x_read;			/* MBAR_ETH + 0x174 */
-
-	uint32 RES7[2];			/* MBAR_ETH + 0x178-17C */
-	uint32 fm_cntrl;		/* MBAR_ETH + 0x180 */
-#define erdsr fm_cntrl
-	uint32 rfifo_data;		/* MBAR_ETH + 0x184 */
-#define etdsr rfifo_data
-	uint32 rfifo_status;		/* MBAR_ETH + 0x188 */
-#define emrbr rfifo_status
-	uint32 rfifo_cntrl;		/* MBAR_ETH + 0x18C */
-	uint32 rfifo_lrf_ptr;		/* MBAR_ETH + 0x190 */
-	uint32 rfifo_lwf_ptr;		/* MBAR_ETH + 0x194 */
-	uint32 rfifo_alarm;		/* MBAR_ETH + 0x198 */
-	uint32 rfifo_rdptr;		/* MBAR_ETH + 0x19C */
-	uint32 rfifo_wrptr;		/* MBAR_ETH + 0x1A0 */
-	uint32 tfifo_data;		/* MBAR_ETH + 0x1A4 */
-	uint32 tfifo_status;		/* MBAR_ETH + 0x1A8 */
-	uint32 tfifo_cntrl;		/* MBAR_ETH + 0x1AC */
-	uint32 tfifo_lrf_ptr;		/* MBAR_ETH + 0x1B0 */
-	uint32 tfifo_lwf_ptr;		/* MBAR_ETH + 0x1B4 */
-	uint32 tfifo_alarm;		/* MBAR_ETH + 0x1B8 */
-	uint32 tfifo_rdptr;		/* MBAR_ETH + 0x1BC */
-	uint32 tfifo_wrptr;		/* MBAR_ETH + 0x1C0 */
-
-	uint32 reset_cntrl;		/* MBAR_ETH + 0x1C4 */
-	uint32 xmit_fsm;		/* MBAR_ETH + 0x1C8 */
-
-	uint32 RES8[3];			/* MBAR_ETH + 0x1CC-1D4 */
-	uint32 rdes_data0;		/* MBAR_ETH + 0x1D8 */
-	uint32 rdes_data1;		/* MBAR_ETH + 0x1DC */
-	uint32 r_length;		/* MBAR_ETH + 0x1E0 */
-	uint32 x_length;		/* MBAR_ETH + 0x1E4 */
-	uint32 x_addr;			/* MBAR_ETH + 0x1E8 */
-	uint32 cdes_data;		/* MBAR_ETH + 0x1EC */
-	uint32 status;			/* MBAR_ETH + 0x1F0 */
-	uint32 dma_control;		/* MBAR_ETH + 0x1F4 */
-	uint32 des_cmnd;		/* MBAR_ETH + 0x1F8 */
-	uint32 data;			/* MBAR_ETH + 0x1FC */
+	volatile uint32 fec_id;			/* MBAR_ETH + 0x000 */
+	volatile uint32 ievent;			/* MBAR_ETH + 0x004 */
+	volatile uint32 imask;			/* MBAR_ETH + 0x008 */
+
+	volatile uint32 RES0[1];		/* MBAR_ETH + 0x00C */
+	volatile uint32 r_des_active;		/* MBAR_ETH + 0x010 */
+	volatile uint32 x_des_active;		/* MBAR_ETH + 0x014 */
+	volatile uint32 r_des_active_cl;	/* MBAR_ETH + 0x018 */
+	volatile uint32 x_des_active_cl;	/* MBAR_ETH + 0x01C */
+	volatile uint32 ivent_set;		/* MBAR_ETH + 0x020 */
+	volatile uint32 ecntrl;			/* MBAR_ETH + 0x024 */
+
+	volatile uint32 RES1[6];		/* MBAR_ETH + 0x028-03C */
+	volatile uint32 mii_data;		/* MBAR_ETH + 0x040 */
+	volatile uint32 mii_speed;		/* MBAR_ETH + 0x044 */
+	volatile uint32 mii_status;		/* MBAR_ETH + 0x048 */
+
+	volatile uint32 RES2[5];		/* MBAR_ETH + 0x04C-05C */
+	volatile uint32 mib_data;		/* MBAR_ETH + 0x060 */
+	volatile uint32 mib_control;		/* MBAR_ETH + 0x064 */
+
+	volatile uint32 RES3[6];		/* MBAR_ETH + 0x068-7C */
+	volatile uint32 r_activate;		/* MBAR_ETH + 0x080 */
+	volatile uint32 r_cntrl;		/* MBAR_ETH + 0x084 */
+	volatile uint32 r_hash;			/* MBAR_ETH + 0x088 */
+	volatile uint32 r_data;			/* MBAR_ETH + 0x08C */
+	volatile uint32 ar_done;		/* MBAR_ETH + 0x090 */
+	volatile uint32 r_test;			/* MBAR_ETH + 0x094 */
+	volatile uint32 r_mib;			/* MBAR_ETH + 0x098 */
+	volatile uint32 r_da_low;		/* MBAR_ETH + 0x09C */
+	volatile uint32 r_da_high;		/* MBAR_ETH + 0x0A0 */
+
+	volatile uint32 RES4[7];		/* MBAR_ETH + 0x0A4-0BC */
+	volatile uint32 x_activate;		/* MBAR_ETH + 0x0C0 */
+	volatile uint32 x_cntrl;		/* MBAR_ETH + 0x0C4 */
+	volatile uint32 backoff;		/* MBAR_ETH + 0x0C8 */
+	volatile uint32 x_data;			/* MBAR_ETH + 0x0CC */
+	volatile uint32 x_status;		/* MBAR_ETH + 0x0D0 */
+	volatile uint32 x_mib;			/* MBAR_ETH + 0x0D4 */
+	volatile uint32 x_test;			/* MBAR_ETH + 0x0D8 */
+	volatile uint32 fdxfc_da1;		/* MBAR_ETH + 0x0DC */
+	volatile uint32 fdxfc_da2;		/* MBAR_ETH + 0x0E0 */
+	volatile uint32 paddr1;			/* MBAR_ETH + 0x0E4 */
+	volatile uint32 paddr2;			/* MBAR_ETH + 0x0E8 */
+	volatile uint32 op_pause;		/* MBAR_ETH + 0x0EC */
+
+	volatile uint32 RES5[4];		/* MBAR_ETH + 0x0F0-0FC */
+	volatile uint32 instr_reg;		/* MBAR_ETH + 0x100 */
+	volatile uint32 context_reg;		/* MBAR_ETH + 0x104 */
+	volatile uint32 test_cntrl;		/* MBAR_ETH + 0x108 */
+	volatile uint32 acc_reg;		/* MBAR_ETH + 0x10C */
+	volatile uint32 ones;			/* MBAR_ETH + 0x110 */
+	volatile uint32 zeros;			/* MBAR_ETH + 0x114 */
+	volatile uint32 iaddr1;			/* MBAR_ETH + 0x118 */
+	volatile uint32 iaddr2;			/* MBAR_ETH + 0x11C */
+	volatile uint32 gaddr1;			/* MBAR_ETH + 0x120 */
+	volatile uint32 gaddr2;			/* MBAR_ETH + 0x124 */
+	volatile uint32 random;			/* MBAR_ETH + 0x128 */
+	volatile uint32 rand1;			/* MBAR_ETH + 0x12C */
+	volatile uint32 tmp;			/* MBAR_ETH + 0x130 */
+
+	volatile uint32 RES6[3];		/* MBAR_ETH + 0x134-13C */
+	volatile uint32 fifo_id;		/* MBAR_ETH + 0x140 */
+	volatile uint32 x_wmrk;			/* MBAR_ETH + 0x144 */
+	volatile uint32 fcntrl;			/* MBAR_ETH + 0x148 */
+	volatile uint32 r_bound;		/* MBAR_ETH + 0x14C */
+	volatile uint32 r_fstart;		/* MBAR_ETH + 0x150 */
+	volatile uint32 r_count;		/* MBAR_ETH + 0x154 */
+	volatile uint32 r_lag;			/* MBAR_ETH + 0x158 */
+	volatile uint32 r_read;			/* MBAR_ETH + 0x15C */
+	volatile uint32 r_write;		/* MBAR_ETH + 0x160 */
+	volatile uint32 x_count;		/* MBAR_ETH + 0x164 */
+	volatile uint32 x_lag;			/* MBAR_ETH + 0x168 */
+	volatile uint32 x_retry;		/* MBAR_ETH + 0x16C */
+	volatile uint32 x_write;		/* MBAR_ETH + 0x170 */
+	volatile uint32 x_read;			/* MBAR_ETH + 0x174 */
+
+	volatile uint32 RES7[2];		/* MBAR_ETH + 0x178-17C */
+	volatile uint32 fm_cntrl;		/* MBAR_ETH + 0x180 */
+	volatile uint32 rfifo_data;		/* MBAR_ETH + 0x184 */
+	volatile uint32 rfifo_status;		/* MBAR_ETH + 0x188 */
+	volatile uint32 rfifo_cntrl;		/* MBAR_ETH + 0x18C */
+	volatile uint32 rfifo_lrf_ptr;		/* MBAR_ETH + 0x190 */
+	volatile uint32 rfifo_lwf_ptr;		/* MBAR_ETH + 0x194 */
+	volatile uint32 rfifo_alarm;		/* MBAR_ETH + 0x198 */
+	volatile uint32 rfifo_rdptr;		/* MBAR_ETH + 0x19C */
+	volatile uint32 rfifo_wrptr;		/* MBAR_ETH + 0x1A0 */
+	volatile uint32 tfifo_data;		/* MBAR_ETH + 0x1A4 */
+	volatile uint32 tfifo_status;		/* MBAR_ETH + 0x1A8 */
+	volatile uint32 tfifo_cntrl;		/* MBAR_ETH + 0x1AC */
+	volatile uint32 tfifo_lrf_ptr;		/* MBAR_ETH + 0x1B0 */
+	volatile uint32 tfifo_lwf_ptr;		/* MBAR_ETH + 0x1B4 */
+	volatile uint32 tfifo_alarm;		/* MBAR_ETH + 0x1B8 */
+	volatile uint32 tfifo_rdptr;		/* MBAR_ETH + 0x1BC */
+	volatile uint32 tfifo_wrptr;		/* MBAR_ETH + 0x1C0 */
+
+	volatile uint32 reset_cntrl;		/* MBAR_ETH + 0x1C4 */
+	volatile uint32 xmit_fsm;		/* MBAR_ETH + 0x1C8 */
+
+	volatile uint32 RES8[3];		/* MBAR_ETH + 0x1CC-1D4 */
+	volatile uint32 rdes_data0;		/* MBAR_ETH + 0x1D8 */
+	volatile uint32 rdes_data1;		/* MBAR_ETH + 0x1DC */
+	volatile uint32 r_length;		/* MBAR_ETH + 0x1E0 */
+	volatile uint32 x_length;		/* MBAR_ETH + 0x1E4 */
+	volatile uint32 x_addr;			/* MBAR_ETH + 0x1E8 */
+	volatile uint32 cdes_data;		/* MBAR_ETH + 0x1EC */
+	volatile uint32 status;			/* MBAR_ETH + 0x1F0 */
+	volatile uint32 dma_control;		/* MBAR_ETH + 0x1F4 */
+	volatile uint32 des_cmnd;		/* MBAR_ETH + 0x1F8 */
+	volatile uint32 data;			/* MBAR_ETH + 0x1FC */
 
 /*  MIB COUNTERS (Offset 200-2FF) */
 
-	uint32 rmon_t_drop;		/* MBAR_ETH + 0x200 */
-	uint32 rmon_t_packets;		/* MBAR_ETH + 0x204 */
-	uint32 rmon_t_bc_pkt;		/* MBAR_ETH + 0x208 */
-	uint32 rmon_t_mc_pkt;		/* MBAR_ETH + 0x20C */
-	uint32 rmon_t_crc_align;	/* MBAR_ETH + 0x210 */
-	uint32 rmon_t_undersize;	/* MBAR_ETH + 0x214 */
-	uint32 rmon_t_oversize;		/* MBAR_ETH + 0x218 */
-	uint32 rmon_t_frag;		/* MBAR_ETH + 0x21C */
-	uint32 rmon_t_jab;		/* MBAR_ETH + 0x220 */
-	uint32 rmon_t_col;		/* MBAR_ETH + 0x224 */
-	uint32 rmon_t_p64;		/* MBAR_ETH + 0x228 */
-	uint32 rmon_t_p65to127;		/* MBAR_ETH + 0x22C */
-	uint32 rmon_t_p128to255;	/* MBAR_ETH + 0x230 */
-	uint32 rmon_t_p256to511;	/* MBAR_ETH + 0x234 */
-	uint32 rmon_t_p512to1023;	/* MBAR_ETH + 0x238 */
-	uint32 rmon_t_p1024to2047;	/* MBAR_ETH + 0x23C */
-	uint32 rmon_t_p_gte2048;	/* MBAR_ETH + 0x240 */
-	uint32 rmon_t_octets;		/* MBAR_ETH + 0x244 */
-	uint32 ieee_t_drop;		/* MBAR_ETH + 0x248 */
-	uint32 ieee_t_frame_ok;		/* MBAR_ETH + 0x24C */
-	uint32 ieee_t_1col;		/* MBAR_ETH + 0x250 */
-	uint32 ieee_t_mcol;		/* MBAR_ETH + 0x254 */
-	uint32 ieee_t_def;		/* MBAR_ETH + 0x258 */
-	uint32 ieee_t_lcol;		/* MBAR_ETH + 0x25C */
-	uint32 ieee_t_excol;		/* MBAR_ETH + 0x260 */
-	uint32 ieee_t_macerr;		/* MBAR_ETH + 0x264 */
-	uint32 ieee_t_cserr;		/* MBAR_ETH + 0x268 */
-	uint32 ieee_t_sqe;		/* MBAR_ETH + 0x26C */
-	uint32 t_fdxfc;			/* MBAR_ETH + 0x270 */
-	uint32 ieee_t_octets_ok;	/* MBAR_ETH + 0x274 */
-
-	uint32 RES9[2];			/* MBAR_ETH + 0x278-27C */
-	uint32 rmon_r_drop;		/* MBAR_ETH + 0x280 */
-	uint32 rmon_r_packets;		/* MBAR_ETH + 0x284 */
-	uint32 rmon_r_bc_pkt;		/* MBAR_ETH + 0x288 */
-	uint32 rmon_r_mc_pkt;		/* MBAR_ETH + 0x28C */
-	uint32 rmon_r_crc_align;	/* MBAR_ETH + 0x290 */
-	uint32 rmon_r_undersize;	/* MBAR_ETH + 0x294 */
-	uint32 rmon_r_oversize;		/* MBAR_ETH + 0x298 */
-	uint32 rmon_r_frag;		/* MBAR_ETH + 0x29C */
-	uint32 rmon_r_jab;		/* MBAR_ETH + 0x2A0 */
-
-	uint32 rmon_r_resvd_0;		/* MBAR_ETH + 0x2A4 */
-
-	uint32 rmon_r_p64;		/* MBAR_ETH + 0x2A8 */
-	uint32 rmon_r_p65to127;		/* MBAR_ETH + 0x2AC */
-	uint32 rmon_r_p128to255;	/* MBAR_ETH + 0x2B0 */
-	uint32 rmon_r_p256to511;	/* MBAR_ETH + 0x2B4 */
-	uint32 rmon_r_p512to1023;	/* MBAR_ETH + 0x2B8 */
-	uint32 rmon_r_p1024to2047;	/* MBAR_ETH + 0x2BC */
-	uint32 rmon_r_p_gte2048;	/* MBAR_ETH + 0x2C0 */
-	uint32 rmon_r_octets;		/* MBAR_ETH + 0x2C4 */
-	uint32 ieee_r_drop;		/* MBAR_ETH + 0x2C8 */
-	uint32 ieee_r_frame_ok;		/* MBAR_ETH + 0x2CC */
-	uint32 ieee_r_crc;		/* MBAR_ETH + 0x2D0 */
-	uint32 ieee_r_align;		/* MBAR_ETH + 0x2D4 */
-	uint32 r_macerr;		/* MBAR_ETH + 0x2D8 */
-	uint32 r_fdxfc;			/* MBAR_ETH + 0x2DC */
-	uint32 ieee_r_octets_ok;	/* MBAR_ETH + 0x2E0 */
-
-	uint32 RES10[6];		/* MBAR_ETH + 0x2E4-2FC */
-
-	uint32 RES11[64];		/* MBAR_ETH + 0x300-3FF */
+	volatile uint32 rmon_t_drop;		/* MBAR_ETH + 0x200 */
+	volatile uint32 rmon_t_packets;		/* MBAR_ETH + 0x204 */
+	volatile uint32 rmon_t_bc_pkt;		/* MBAR_ETH + 0x208 */
+	volatile uint32 rmon_t_mc_pkt;		/* MBAR_ETH + 0x20C */
+	volatile uint32 rmon_t_crc_align;	/* MBAR_ETH + 0x210 */
+	volatile uint32 rmon_t_undersize;	/* MBAR_ETH + 0x214 */
+	volatile uint32 rmon_t_oversize;	/* MBAR_ETH + 0x218 */
+	volatile uint32 rmon_t_frag;		/* MBAR_ETH + 0x21C */
+	volatile uint32 rmon_t_jab;		/* MBAR_ETH + 0x220 */
+	volatile uint32 rmon_t_col;		/* MBAR_ETH + 0x224 */
+	volatile uint32 rmon_t_p64;		/* MBAR_ETH + 0x228 */
+	volatile uint32 rmon_t_p65to127;	/* MBAR_ETH + 0x22C */
+	volatile uint32 rmon_t_p128to255;	/* MBAR_ETH + 0x230 */
+	volatile uint32 rmon_t_p256to511;	/* MBAR_ETH + 0x234 */
+	volatile uint32 rmon_t_p512to1023;	/* MBAR_ETH + 0x238 */
+	volatile uint32 rmon_t_p1024to2047;	/* MBAR_ETH + 0x23C */
+	volatile uint32 rmon_t_p_gte2048;	/* MBAR_ETH + 0x240 */
+	volatile uint32 rmon_t_octets;		/* MBAR_ETH + 0x244 */
+	volatile uint32 ieee_t_drop;		/* MBAR_ETH + 0x248 */
+	volatile uint32 ieee_t_frame_ok;	/* MBAR_ETH + 0x24C */
+	volatile uint32 ieee_t_1col;		/* MBAR_ETH + 0x250 */
+	volatile uint32 ieee_t_mcol;		/* MBAR_ETH + 0x254 */
+	volatile uint32 ieee_t_def;		/* MBAR_ETH + 0x258 */
+	volatile uint32 ieee_t_lcol;		/* MBAR_ETH + 0x25C */
+	volatile uint32 ieee_t_excol;		/* MBAR_ETH + 0x260 */
+	volatile uint32 ieee_t_macerr;		/* MBAR_ETH + 0x264 */
+	volatile uint32 ieee_t_cserr;		/* MBAR_ETH + 0x268 */
+	volatile uint32 ieee_t_sqe;		/* MBAR_ETH + 0x26C */
+	volatile uint32 t_fdxfc;		/* MBAR_ETH + 0x270 */
+	volatile uint32 ieee_t_octets_ok;	/* MBAR_ETH + 0x274 */
+
+	volatile uint32 RES9[2];		/* MBAR_ETH + 0x278-27C */
+	volatile uint32 rmon_r_drop;		/* MBAR_ETH + 0x280 */
+	volatile uint32 rmon_r_packets;		/* MBAR_ETH + 0x284 */
+	volatile uint32 rmon_r_bc_pkt;		/* MBAR_ETH + 0x288 */
+	volatile uint32 rmon_r_mc_pkt;		/* MBAR_ETH + 0x28C */
+	volatile uint32 rmon_r_crc_align;	/* MBAR_ETH + 0x290 */
+	volatile uint32 rmon_r_undersize;	/* MBAR_ETH + 0x294 */
+	volatile uint32 rmon_r_oversize;	/* MBAR_ETH + 0x298 */
+	volatile uint32 rmon_r_frag;		/* MBAR_ETH + 0x29C */
+	volatile uint32 rmon_r_jab;		/* MBAR_ETH + 0x2A0 */
+
+	volatile uint32 rmon_r_resvd_0;		/* MBAR_ETH + 0x2A4 */
+
+	volatile uint32 rmon_r_p64;		/* MBAR_ETH + 0x2A8 */
+	volatile uint32 rmon_r_p65to127;	/* MBAR_ETH + 0x2AC */
+	volatile uint32 rmon_r_p128to255;	/* MBAR_ETH + 0x2B0 */
+	volatile uint32 rmon_r_p256to511;	/* MBAR_ETH + 0x2B4 */
+	volatile uint32 rmon_r_p512to1023;	/* MBAR_ETH + 0x2B8 */
+	volatile uint32 rmon_r_p1024to2047;	/* MBAR_ETH + 0x2BC */
+	volatile uint32 rmon_r_p_gte2048;	/* MBAR_ETH + 0x2C0 */
+	volatile uint32 rmon_r_octets;		/* MBAR_ETH + 0x2C4 */
+	volatile uint32 ieee_r_drop;		/* MBAR_ETH + 0x2C8 */
+	volatile uint32 ieee_r_frame_ok;	/* MBAR_ETH + 0x2CC */
+	volatile uint32 ieee_r_crc;		/* MBAR_ETH + 0x2D0 */
+	volatile uint32 ieee_r_align;		/* MBAR_ETH + 0x2D4 */
+	volatile uint32 r_macerr;		/* MBAR_ETH + 0x2D8 */
+	volatile uint32 r_fdxfc;		/* MBAR_ETH + 0x2DC */
+	volatile uint32 ieee_r_octets_ok;	/* MBAR_ETH + 0x2E0 */
+
+	volatile uint32 RES10[6];		/* MBAR_ETH + 0x2E4-2FC */
+
+	volatile uint32 RES11[64];		/* MBAR_ETH + 0x300-3FF */
 } ethernet_regs;
 
 #define FEC_IEVENT_HBERR                0x80000000
@@ -245,12 +239,8 @@ typedef struct ethernet_register_set {
 #define FEC_ECNTRL_RESET                0x00000001
 #define FEC_ECNTRL_ETHER_EN             0x00000002
 
-#ifdef CONFIG_MPC5200
-/**
- * Receive & Transmit Buffer Descriptor definitions
- * Big endian layout
- */
-typedef struct {
+/* Receive & Transmit Buffer Descriptor definitions */
+typedef struct BufferDescriptor {
 	uint16 status;
 	uint16 dataLength;
 	uint32 dataPointer;
@@ -261,58 +251,33 @@ typedef struct {
 	uint16 dataLength;
 	uint32 dataPointer;
 } FEC_TBD;
-#endif
 
-#ifdef CONFIG_ARCH_IMX27
-/**
- * Receive & Transmit Buffer Descriptor definitions
- * Little endian layout
- */
-typedef struct {
-	uint16 dataLength;
-	uint16 status;
-	uint32 dataPointer;
-} FEC_RBD;
-
-typedef struct {
-	uint16 dataLength;
-	uint16 status;
-	uint32 dataPointer;
-} FEC_TBD;
-#endif
+/* private structure */
 
-/**
- * private structure
- */
 typedef struct {
 	ethernet_regs *eth;
-	xceiver_type xcv_type;		/** transceiver type */
-	FEC_RBD *rbdBase;		/** RBD ring */
-	FEC_TBD *tbdBase;		/** TBD ring */
-	uint16 rbdIndex;		/** next receive BD to read */
+	xceiver_type xcv_type;		/* transceiver type */
+	FEC_RBD *rbdBase;		/* RBD ring */
+	FEC_TBD *tbdBase;		/* TBD ring */
+	uint16 rbdIndex;		/* next receive BD to read */
+	uint16 tbdIndex;		/* next transmit BD to send */
+	uint16 usedTbdIndex;		/* next transmit BD to clean */
+	uint16 cleanTbdNum;		/* the number of available transmit BDs */
 
 	struct miiphy_device miiphy;
 } mpc5xxx_fec_priv;
 
-/**
- * buffer alignment on request
- */
-#define RDB_ALIGNMENT 16
-
 /* Ethernet parameter area */
 #define FEC_TBD_BASE		(FEC_PARAM_BASE + 0x00)
 #define FEC_TBD_NEXT		(FEC_PARAM_BASE + 0x04)
 #define FEC_RBD_BASE		(FEC_PARAM_BASE + 0x08)
 #define FEC_RBD_NEXT		(FEC_PARAM_BASE + 0x0c)
 
-/**
- * Numbers of buffer descriptos for receiving
- */
-#define FEC_RBD_NUM		64	/* The user can adjust this value */
+/* BD Numer definitions */
+#define FEC_TBD_NUM		48	/* The user can adjust this value */
+#define FEC_RBD_NUM		32	/* The user can adjust this value */
 
-/**
- * define the packet size limit
- */
+/* packet size limit */
 #define FEC_MAX_PKT_SIZE	1536
 
 /* RBD bits definitions */
@@ -353,8 +318,3 @@ typedef struct {
 #define FEC_MII_DATA_PA_SHIFT	23	/* MII PHY address bits */
 
 #endif	/* __MPC5XXX_FEC_H */
-
-/**
- * @file
- * @brief Definitions for the FEC driver (MPC52xx and i-MX27)
- */