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| author | Andrey Smirnov <andrew.smirnov@gmail.com> | 2015-12-31 21:58:38 -0800 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2016-01-08 08:51:53 +0100 |
| commit | 2cc01b1eed5f111eabb06b339748a63b0189a4ee (patch) | |
| tree | 3bfcd249d715e2064ffb7ddf68296ae1948e192a /drivers/pci/pci-imx6.c | |
| parent | cb3643d425f3d83748a67a0fec973512a5ea5956 (diff) | |
| download | barebox-2cc01b1eed5f111eabb06b339748a63b0189a4ee.tar.gz barebox-2cc01b1eed5f111eabb06b339748a63b0189a4ee.tar.xz | |
i.MX6: pci: Avoid aborts when asserting PCIe reset
When booting Barebox in the HW environment where PCIe core has been
used but not properly shut down, writing to PCIE_PL_PFLR in
imx6_pcie_assert_core_reset would cause data abort exception.
The problem can be easily reproduced on a i.MX6 based board with PCIe
slot populated with some device by doing:
> bootm -f -e 0x1050 <your board's>.img
Ignoring this exception seem to allow PCIe core to successfully
initialize and enumerate devices properly. This is also how Linux
Kernel version of the driver handles this situation -- it installs
dummy no-op abort handler at the beginning of device's probing.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/pci/pci-imx6.c')
| -rw-r--r-- | drivers/pci/pci-imx6.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/pci/pci-imx6.c b/drivers/pci/pci-imx6.c index 713007b27a..3a3edd8e21 100644 --- a/drivers/pci/pci-imx6.c +++ b/drivers/pci/pci-imx6.c @@ -13,6 +13,7 @@ #include <common.h> #include <clock.h> +#include <abort.h> #include <malloc.h> #include <io.h> #include <init.h> @@ -237,7 +238,10 @@ static int imx6_pcie_assert_core_reset(struct pcie_port *pp) val = readl(pp->dbi_base + PCIE_PL_PFLR); val &= ~PCIE_PL_PFLR_LINK_STATE_MASK; val |= PCIE_PL_PFLR_FORCE_LINK; + + data_abort_mask(); writel(val, pp->dbi_base + PCIE_PL_PFLR); + data_abort_unmask(); gpr12 &= ~IMX6Q_GPR12_PCIE_CTL_2; writel(gpr12, imx6_pcie->iomuxc_gpr + IOMUXC_GPR12); |