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authorLucas Stach <l.stach@pengutronix.de>2016-11-01 09:58:53 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2016-11-03 07:12:10 +0100
commit18ee9aade879f0a48a1785ef3922d0e8738b9027 (patch)
treefbd3c32ebbc794c301fe884962752d825600f246 /drivers/pci/pci.c
parent9c29edf10bd44514acfddf86ff169e243ac206a4 (diff)
downloadbarebox-18ee9aade879f0a48a1785ef3922d0e8738b9027.tar.gz
barebox-18ee9aade879f0a48a1785ef3922d0e8738b9027.tar.xz
PCI: align address range before scanning bridge
Otherwise we may end up with a too low base address and push requests for the upstream bus onto the downstream side. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/pci/pci.c')
-rw-r--r--drivers/pci/pci.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index eb3ce0f321..19cda1f145 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -252,6 +252,7 @@ static void prescan_setup_bridge(struct pci_dev *dev)
if (last_mem) {
/* Set up memory and I/O filter limits, assume 32-bit I/O space */
+ last_mem = ALIGN(last_mem, SZ_1M);
pci_write_config_word(dev, PCI_MEMORY_BASE,
(last_mem & 0xfff00000) >> 16);
cmdstat |= PCI_COMMAND_MEMORY;
@@ -259,6 +260,7 @@ static void prescan_setup_bridge(struct pci_dev *dev)
if (last_mem_pref) {
/* Set up memory and I/O filter limits, assume 32-bit I/O space */
+ last_mem_pref = ALIGN(last_mem_pref, SZ_1M);
pci_write_config_word(dev, PCI_PREF_MEMORY_BASE,
(last_mem_pref & 0xfff00000) >> 16);
cmdstat |= PCI_COMMAND_MEMORY;
@@ -270,6 +272,7 @@ static void prescan_setup_bridge(struct pci_dev *dev)
}
if (last_io) {
+ last_io = ALIGN(last_io, SZ_4K);
pci_write_config_byte(dev, PCI_IO_BASE,
(last_io & 0x0000f000) >> 8);
pci_write_config_word(dev, PCI_IO_BASE_UPPER16,