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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2015-02-26 14:11:45 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2015-03-17 07:36:00 +0100 |
| commit | 467bc67bc30e21cd92f1810a6e3a8c317e79b78c (patch) | |
| tree | ac1bccfa601595780577c8a44db419a4dbb2b17f /drivers/pci/pcie-designware.h | |
| parent | 025362e2cc2546aa0ae5e663e0dd7ce3efd44cac (diff) | |
| download | barebox-467bc67bc30e21cd92f1810a6e3a8c317e79b78c.tar.gz barebox-467bc67bc30e21cd92f1810a6e3a8c317e79b78c.tar.xz | |
pci: Add pcie-designware driver
Based on the corresponding kernel driver, only small changes
to make it work on barebox.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/pci/pcie-designware.h')
| -rw-r--r-- | drivers/pci/pcie-designware.h | 71 |
1 files changed, 71 insertions, 0 deletions
diff --git a/drivers/pci/pcie-designware.h b/drivers/pci/pcie-designware.h new file mode 100644 index 0000000000..8d0330a5a1 --- /dev/null +++ b/drivers/pci/pcie-designware.h @@ -0,0 +1,71 @@ +/* + * Synopsys Designware PCIe host controller driver + * + * Copyright (C) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Author: Jingoo Han <jg1.han@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _PCIE_DESIGNWARE_H +#define _PCIE_DESIGNWARE_H + +struct pcie_port { + struct device_d *dev; + u8 root_bus_nr; + void __iomem *dbi_base; + u64 cfg0_base; + u64 cfg0_mod_base; + void __iomem *va_cfg0_base; + u32 cfg0_size; + u64 cfg1_base; + u64 cfg1_mod_base; + void __iomem *va_cfg1_base; + u32 cfg1_size; + u64 io_base; + u64 io_mod_base; + phys_addr_t io_bus_addr; + u32 io_size; + u64 mem_base; + u64 mem_mod_base; + phys_addr_t mem_bus_addr; + u32 mem_size; + struct resource cfg; + struct resource io; + struct resource mem; + struct resource busn; + int irq; + u32 lanes; + struct pcie_host_ops *ops; + struct pci_controller pci; +}; + +struct pcie_host_ops { + void (*readl_rc)(struct pcie_port *pp, + void __iomem *dbi_base, u32 *val); + void (*writel_rc)(struct pcie_port *pp, + u32 val, void __iomem *dbi_base); + int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val); + int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val); + int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus, + unsigned int devfn, int where, int size, u32 *val); + int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus, + unsigned int devfn, int where, int size, u32 val); + int (*link_up)(struct pcie_port *pp); + void (*host_init)(struct pcie_port *pp); + void (*scan_bus)(struct pcie_port *pp); +}; + +int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val); +int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val); +irqreturn_t dw_handle_msi_irq(struct pcie_port *pp); +void dw_pcie_msi_init(struct pcie_port *pp); +int dw_pcie_link_up(struct pcie_port *pp); +void dw_pcie_setup_rc(struct pcie_port *pp); +int dw_pcie_host_init(struct pcie_port *pp); + +#endif /* _PCIE_DESIGNWARE_H */ |