PCI: designware: Simplify dw_pcie_cfg_read/write() interfaces

Port of a Linux commit 4c45852f494dab827291c656ee9e12f3f4ee64d6

  Callers of dw_pcie_cfg_read() and dw_pcie_cfg_write() previously had to
  split the address into "addr" and "where".  The callees assumed "addr" was
  32-bit aligned (with zeros in the low two bits) and they used only the low
  two bits of "where".

  Accept the entire address in "addr" and drop the now-redundant "where"
  argument.  As an example, this replaces this:

    int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
      *val = readb(addr + (where & 1));

  with this:

    int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
      *val = readb(addr):

  [bhelgaas: changelog, split access size change to separate patch]
  Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

TODO: Fixup the pcie-designware.h

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

1 files changed, 2 insertions, 2 deletions

diff --git a/drivers/pci/pcie-designware.h b/drivers/pci/pcie-designware.h
index ba5752ec1a..b8b85c575d 100644
--- a/drivers/pci/pcie-designware.h
+++ b/drivers/pci/pcie-designware.h
@@ -60,8 +60,8 @@ struct pcie_host_ops {
 	void (*scan_bus)(struct pcie_port *pp);
 };
 
-int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);
-int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);
+int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val);
+int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val);
 int dw_pcie_link_up(struct pcie_port *pp);
 void dw_pcie_setup_rc(struct pcie_port *pp);
 int dw_pcie_host_init(struct pcie_port *pp);