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author | Andrey Smirnov <andrew.smirnov@gmail.com> | 2018-12-16 21:18:25 -0800 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-01-08 16:28:47 +0100 |
commit | 7f46d5f95dc986ecb3fa90f17767c0f394ff60b6 (patch) | |
tree | d461f0b12f88aa692990ec6269bee058cef5ad63 /drivers/pci | |
parent | 58a50528219fa419631a8e520384e4d68b39a35d (diff) | |
download | barebox-7f46d5f95dc986ecb3fa90f17767c0f394ff60b6.tar.gz barebox-7f46d5f95dc986ecb3fa90f17767c0f394ff60b6.tar.xz |
PCI: designware: Use exact access size in dw_pcie_cfg_read()
Port of a Linux commit c003ca99632e1783466f459033874a0e1e31457b
dw_pcie_cfg_write() uses the exact 8-, 16-, or 32-bit access size
requested, but dw_pcie_cfg_read() previously performed a 32-bit read and
masked out the bits requested.
Use the exact access size in dw_pcie_cfg_read(). For example, if we want
an 8-bit read, use readb() instead of using readl() and masking out the 8
bits we need. This makes it symmetric with dw_pcie_cfg_write().
[bhelgaas: split into separate patch, set *val = 0 in failure case]
Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
NOTE: Original Linux commit incorrectly handles the case of single
byte read by doing
else if (size == 1)
*val = readb(addr + (where & 1));
instead of
else if (size == 1)
*val = readb(addr + (where & 3));
which would be symmetric with what's done in dw_pcie_cfg_write(). This
was most likely overlooked since commit that follow change the
signature of the function, remove 'where' as argument completely,
inadvertenly fixing the problem.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/pci')
-rw-r--r-- | drivers/pci/pcie-designware.c | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/drivers/pci/pcie-designware.c b/drivers/pci/pcie-designware.c index 547d402a7d..bda85c30e4 100644 --- a/drivers/pci/pcie-designware.c +++ b/drivers/pci/pcie-designware.c @@ -76,14 +76,16 @@ static unsigned long global_io_offset; int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val) { - *val = readl(addr); - - if (size == 1) - *val = (*val >> (8 * (where & 3))) & 0xff; + if (size == 4) + *val = readl(addr); else if (size == 2) - *val = (*val >> (8 * (where & 3))) & 0xffff; - else if (size != 4) + *val = readw(addr + (where & 2)); + else if (size == 1) + *val = readb(addr + (where & 3)); + else { + *val = 0; return PCIBIOS_BAD_REGISTER_NUMBER; + } return PCIBIOS_SUCCESSFUL; } |