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| author | Andrey Smirnov <andrew.smirnov@gmail.com> | 2018-12-16 21:18:28 -0800 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-01-08 16:28:47 +0100 |
| commit | c76c0cb4d8bf127b05a74ff18efe94e2e97efae3 (patch) | |
| tree | 1ef1d49e96796b2bd3aceb7f69e06d69382eed58 /drivers/pci | |
| parent | fced0699b549c30a36c733f5648ccb77f6bfe644 (diff) | |
| download | barebox-c76c0cb4d8bf127b05a74ff18efe94e2e97efae3.tar.gz barebox-c76c0cb4d8bf127b05a74ff18efe94e2e97efae3.tar.xz | |
PCI: designware: Make "num-lanes" an optional DT property
Port of a Linux commit 907fce0902539ecde609e485eb2ecd7119a7a623
Currently "num-lanes" is read in dw_pcie_host_init(), but it is only used
if we call dw_pcie_setup_rc() while bringing up the link. If the link has
already been brought up by firmware, we need not call dw_pcie_setup_rc(),
and "num-lanes" is unnecessary.
Only complain about "num-lanes" if we actually need it and we didn't find a
valid value.
[bhelgaas: changelog]
Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/pcie-designware.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/drivers/pci/pcie-designware.c b/drivers/pci/pcie-designware.c index f47e5eb1e4..977548f013 100644 --- a/drivers/pci/pcie-designware.c +++ b/drivers/pci/pcie-designware.c @@ -203,7 +203,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp) struct resource *cfg_res; u32 val, na, ns; const __be32 *addrp; - int index; + int index, ret; /* Find the address cell size and the number of cells in order to get * the untranslated address. @@ -285,10 +285,9 @@ int __init dw_pcie_host_init(struct pcie_port *pp) if (!pp->va_cfg1_base) pp->va_cfg1_base = (void __force *)(u32)pp->cfg1_base; - if (of_property_read_u32(np, "num-lanes", &pp->lanes)) { - dev_err(pp->dev, "Failed to parse the number of lanes\n"); - return -EINVAL; - } + ret = of_property_read_u32(np, "num-lanes", &pp->lanes); + if (ret) + pp->lanes = 0; if (pp->ops->host_init) pp->ops->host_init(pp); @@ -496,6 +495,9 @@ void dw_pcie_setup_rc(struct pcie_port *pp) case 4: val |= PORT_LINK_MODE_4_LANES; break; + default: + dev_err(pp->dev, "num-lanes %u: invalid value\n", pp->lanes); + return; } dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL); |