diff options
| author | Lucas Stach <dev@lynxeye.de> | 2015-04-29 21:59:48 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2015-05-01 08:37:40 +0200 |
| commit | f6842f2e8bd0d0906c1d8e953dae598398388232 (patch) | |
| tree | fbef37811883881d2a9ec976d52584b06c385ff3 /drivers/pci | |
| parent | 9496896fbf07da4a8f3597c9b293b0bc0c32c5a9 (diff) | |
| download | barebox-f6842f2e8bd0d0906c1d8e953dae598398388232.tar.gz barebox-f6842f2e8bd0d0906c1d8e953dae598398388232.tar.xz | |
PCI: imx6: simplify config access code
The PCI core fills in the primary bus number, so there is no
need to walk up the PCI hierarchy in the driver manually.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/pcie-designware.c | 11 |
1 files changed, 2 insertions, 9 deletions
diff --git a/drivers/pci/pcie-designware.c b/drivers/pci/pcie-designware.c index 4edaede10f..4962a19649 100644 --- a/drivers/pci/pcie-designware.c +++ b/drivers/pci/pcie-designware.c @@ -350,13 +350,6 @@ static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp) dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); } -struct pci_bus *get_parent_bus(struct pci_bus *bus) -{ - struct pci_dev *bridge = container_of(bus->parent, struct pci_dev, dev); - - return bridge->bus; -} - static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) { @@ -367,7 +360,7 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, PCIE_ATU_FUNC(PCI_FUNC(devfn)); address = where & ~0x3; - if (get_parent_bus(bus)->number == pp->root_bus_nr) { + if (bus->primary == pp->root_bus_nr) { dw_pcie_prog_viewport_cfg0(pp, busdev); ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size, val); @@ -392,7 +385,7 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, PCIE_ATU_FUNC(PCI_FUNC(devfn)); address = where & ~0x3; - if (get_parent_bus(bus)->number == pp->root_bus_nr) { + if (bus->primary == pp->root_bus_nr) { dw_pcie_prog_viewport_cfg0(pp, busdev); ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size, val); |