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| author | Andrey Smirnov <andrew.smirnov@gmail.com> | 2018-12-16 21:19:09 -0800 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-01-08 16:28:48 +0100 |
| commit | 90c2e60f3f2945aca47636059b142c147882f4ed (patch) | |
| tree | 8dcffe047291e39612bcc4ef35897115a977a50d /drivers/pci | |
| parent | 8f5058f90bd4481a7df8f2bae4022f3888eacb46 (diff) | |
| download | barebox-90c2e60f3f2945aca47636059b142c147882f4ed.tar.gz barebox-90c2e60f3f2945aca47636059b142c147882f4ed.tar.xz | |
PCI: dwc: designware: Parse "num-lanes" property in dw_pcie_setup_rc()
Port of a Linux commit 5f334db665173facf2213854408bb5fa2445d0b3
The "num-lanes" DT property is parsed in dw_pcie_host_init(). However
num-lanes is applicable to both root complex mode and endpoint mode. As a
first step, move the parsing of this property outside dw_pcie_host_init().
This is in preparation for splitting pcie-designware.c to pcie-designware.c
and pcie-designware-host.c
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/pcie-designware.c | 18 | ||||
| -rw-r--r-- | drivers/pci/pcie-designware.h | 1 |
2 files changed, 11 insertions, 8 deletions
diff --git a/drivers/pci/pcie-designware.c b/drivers/pci/pcie-designware.c index f440462457..59884d5145 100644 --- a/drivers/pci/pcie-designware.c +++ b/drivers/pci/pcie-designware.c @@ -332,10 +332,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp) if (!pp->va_cfg1_base) pp->va_cfg1_base = (void __force *)(u32)pp->cfg1_base; - ret = of_property_read_u32(np, "num-lanes", &pci->lanes); - if (ret) - pci->lanes = 0; - ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport); if (ret) pci->num_viewport = 2; @@ -521,13 +517,21 @@ static struct pci_ops dw_pcie_ops = { void dw_pcie_setup_rc(struct pcie_port *pp) { + int ret; + u32 lanes; u32 val; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct device_d *dev = pci->dev; + struct device_node *np = dev->device_node; + + ret = of_property_read_u32(np, "num-lanes", &lanes); + if (ret) + lanes = 0; /* set the number of lanes */ val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); val &= ~PORT_LINK_MODE_MASK; - switch (pci->lanes) { + switch (lanes) { case 1: val |= PORT_LINK_MODE_1_LANES; break; @@ -538,7 +542,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp) val |= PORT_LINK_MODE_4_LANES; break; default: - dev_err(pci->dev, "num-lanes %u: invalid value\n", pci->lanes); + dev_err(pci->dev, "num-lanes %u: invalid value\n", lanes); return; } dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); @@ -546,7 +550,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp) /* set link width speed control register */ val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); val &= ~PORT_LOGIC_LINK_WIDTH_MASK; - switch (pci->lanes) { + switch (lanes) { case 1: val |= PORT_LOGIC_LINK_WIDTH_1_LANES; break; diff --git a/drivers/pci/pcie-designware.h b/drivers/pci/pcie-designware.h index b1b8e05544..06d8c769c6 100644 --- a/drivers/pci/pcie-designware.h +++ b/drivers/pci/pcie-designware.h @@ -142,7 +142,6 @@ struct dw_pcie_ops { struct dw_pcie { struct device_d *dev; void __iomem *dbi_base; - u32 lanes; u32 num_viewport; u8 iatu_unroll_enabled; struct pcie_port pp; |